Re: [PATCH v2 1/1] MIPS: lantiq: enable all hardware interrupts on second VPE

[Thomas Bogendoerfer]

On Wed, Sep 21, 2022 at 10:59:44PM +0200, Aleksander Jan Bajkowski wrote:
> This patch is needed to handle interrupts by the second VPE on the Lantiq
> ARX100, xRX200, xRX300 and xRX330 SoCs. Switching some ICU interrupts to
> the second VPE results in a hang. Currently, the vsmp_init_secondary()
> function is responsible for enabling these interrupts. It only enables
> Malta-specific interrupts (SW0, SW1, HW4 and HW5).
> 
> The MIPS core has 8 interrupts defined. On Lantiq SoCs, hardware
> interrupts are wired to an ICU instance. Each VPE has an independent
> instance of the ICU. The mapping of the ICU interrupts is shown below:
> SW0(IP0) - IPI call,
> SW1(IP1) - IPI resched,
> HW0(IP2) - ICU 0-31,
> HW1(IP3) - ICU 32-63,
> HW2(IP4) - ICU 64-95,
> HW3(IP5) - ICU 96-127,
> HW4(IP6) - ICU 128-159,
> HW5(IP7) - timer.
> 
> This patch enables all interrupt lines on the second VPE.
> 
> This problem affects multithreaded SoCs with a custom interrupt controller.
> SOCs with 1004Kc core and newer use the MIPS GIC. At this point, I am aware
> that the Realtek RTL839x and RTL930x SoCs may need a similar fix. In the
> future, this may be replaced with some generic solution.
> 
> Tested on Lantiq xRX200.
> 
> Suggested-by: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>
> Signed-off-by: Aleksander Jan Bajkowski <olek2@xxxxx>
> ---
>  arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

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