Re: [PATCH v2 2/9] dt-bindings: clock: Add bindings for Exynos850 CMU_IS

From: Chanwoo Choi
Date: Wed Aug 17 2022 - 15:34:40 EST


On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. Add
> clock indices and bindings documentation for CMU_IS domain.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> ---
> Changes in v2:
> - (none)
>
> .../clock/samsung,exynos850-clock.yaml | 25 ++++++++++++
> include/dt-bindings/clock/exynos850.h | 40 ++++++++++++++++++-
> 2 files changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> index 53511f056251..7f2e0b1c764c 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -38,6 +38,7 @@ properties:
> - samsung,exynos850-cmu-core
> - samsung,exynos850-cmu-dpu
> - samsung,exynos850-cmu-hsi
> + - samsung,exynos850-cmu-is
> - samsung,exynos850-cmu-peri
>
> clocks:
> @@ -191,6 +192,30 @@ allOf:
> - const: dout_hsi_mmc_card
> - const: dout_hsi_usb20drd
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos850-cmu-is
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_IS bus clock (from CMU_TOP)
> + - description: Image Texture Processing core clock (from CMU_TOP)
> + - description: Visual Recognition Accelerator clock (from CMU_TOP)
> + - description: Geometric Distortion Correction clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_is_bus
> + - const: dout_is_itp
> + - const: dout_is_vra
> + - const: dout_is_gdc
> +
> - if:
> properties:
> compatible:
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 3dc55d4e5b9e..f8bf26f118c1 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -61,7 +61,19 @@
> #define CLK_MOUT_AUD 49
> #define CLK_GOUT_AUD 50
> #define CLK_DOUT_AUD 51
> -#define TOP_NR_CLK 52
> +#define CLK_MOUT_IS_BUS 52
> +#define CLK_MOUT_IS_ITP 53
> +#define CLK_MOUT_IS_VRA 54
> +#define CLK_MOUT_IS_GDC 55
> +#define CLK_GOUT_IS_BUS 56
> +#define CLK_GOUT_IS_ITP 57
> +#define CLK_GOUT_IS_VRA 58
> +#define CLK_GOUT_IS_GDC 59
> +#define CLK_DOUT_IS_BUS 60
> +#define CLK_DOUT_IS_ITP 61
> +#define CLK_DOUT_IS_VRA 62
> +#define CLK_DOUT_IS_GDC 63
> +#define TOP_NR_CLK 64
>
> /* CMU_APM */
> #define CLK_RCO_I3C_PMIC 1
> @@ -187,6 +199,32 @@
> #define CLK_GOUT_SYSREG_HSI_PCLK 13
> #define HSI_NR_CLK 14
>
> +/* CMU_IS */
> +#define CLK_MOUT_IS_BUS_USER 1
> +#define CLK_MOUT_IS_ITP_USER 2
> +#define CLK_MOUT_IS_VRA_USER 3
> +#define CLK_MOUT_IS_GDC_USER 4
> +#define CLK_DOUT_IS_BUSP 5
> +#define CLK_GOUT_IS_CMU_IS_PCLK 6
> +#define CLK_GOUT_IS_CSIS0_ACLK 7
> +#define CLK_GOUT_IS_CSIS1_ACLK 8
> +#define CLK_GOUT_IS_CSIS2_ACLK 9
> +#define CLK_GOUT_IS_TZPC_PCLK 10
> +#define CLK_GOUT_IS_CSIS_DMA_CLK 11
> +#define CLK_GOUT_IS_GDC_CLK 12
> +#define CLK_GOUT_IS_IPP_CLK 13
> +#define CLK_GOUT_IS_ITP_CLK 14
> +#define CLK_GOUT_IS_MCSC_CLK 15
> +#define CLK_GOUT_IS_VRA_CLK 16
> +#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
> +#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
> +#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
> +#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
> +#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
> +#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
> +#define CLK_GOUT_IS_SYSREG_PCLK 23
> +#define IS_NR_CLK 24
> +
> /* CMU_PERI */
> #define CLK_MOUT_PERI_BUS_USER 1
> #define CLK_MOUT_PERI_UART_USER 2


Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>


--
Best Regards,
Samsung Electronics
Chanwoo Choi