RE: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI device

[Mahapatra, Amit Kumar]

Hello Mark,

> -----Original Message-----
> From: Mark Brown <broonie@xxxxxxxxxx>
> Sent: Tuesday, July 19, 2022 11:23 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@xxxxxxx>
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xxxxxxxxxx>;
> p.yadav@xxxxxx; miquel.raynal@xxxxxxxxxxx; richard@xxxxxx;
> vigneshr@xxxxxx; git@xxxxxxxxxx; michal.simek@xxxxxxxxxx; linux-
> spi@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; michael@xxxxxxxx; linux-mtd@xxxxxxxxxxxxxxxxxxx;
> git (AMD-Xilinx) <git@xxxxxxx>
> Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
> device
> 
> On Tue, Jul 19, 2022 at 01:21:41PM +0000, Mahapatra, Amit Kumar wrote:
> 
> > I agree, so for checking the controller multiple chip select
> > capability(using more than one chip select at once) we can define a
> > new spi controller DT property like "multi-cs-cap"(please suggest a better
> name).
> > The controller that can support multiple chip selects should have this
> > property in the spi controller DT node. The spi core will check
> > ctlr->multi-cs-cap to operate multiple chip select in parallel.
> 
> I'm not sure this needs to be a DT property, it's more just something we infer
> from the compatible.  The name seems fine, as does the flag in the controller
> data.

I agree that we can infer this from the compatible and set the flag in the controller data.

> 
> > > the chip selects are available and that the controller can do
> > > something useful with them (and probably have an implementation in
> > > the core for doing so via GPIO).
> 
> > Here are you referring to the usecase in which a controller
> > implementing multi CS support using GPIO?
> 
> Yes, we probably ought to.

In my next version I will add the implementation in the spi core for multi CS support using GPIO, but I will not be able test it as I don't have the necessary hardware setup .

Regards,
Amit