[PATCH v3] ASoC: dt-bindings: fsl,micfil: Convert format to json-schema

From: Shengjiu Wang
Date: Mon Jun 27 2022 - 23:28:22 EST


Convert the NXP MICFIL binding to DT schema format using json-schema.

Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx>
---
changes in v3
- fix the issue with make dtbs_check

changes in v2
- add decription of interrupts.

.../devicetree/bindings/sound/fsl,micfil.txt | 33 -------
.../devicetree/bindings/sound/fsl,micfil.yaml | 85 +++++++++++++++++++
2 files changed, 85 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/fsl,micfil.txt
create mode 100644 Documentation/devicetree/bindings/sound/fsl,micfil.yaml

diff --git a/Documentation/devicetree/bindings/sound/fsl,micfil.txt b/Documentation/devicetree/bindings/sound/fsl,micfil.txt
deleted file mode 100644
index 1ea05d4996c7..000000000000
--- a/Documentation/devicetree/bindings/sound/fsl,micfil.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-NXP MICFIL Digital Audio Interface (MICFIL).
-
-The MICFIL digital interface provides a 16-bit audio signal from a PDM
-microphone bitstream in a configurable output sampling rate.
-
-Required properties:
-
- - compatible : Compatible list, contains "fsl,imx8mm-micfil"
- or "fsl,imx8mp-micfil"
-
- - reg : Offset and length of the register set for the device.
-
- - interrupts : Contains the micfil interrupts.
-
- - clocks : Must contain an entry for each entry in clock-names.
-
- - clock-names : Must include the "ipg_clk" for register access and
- "ipg_clk_app" for internal micfil clock.
-
- - dmas : Generic dma devicetree binding as described in
- Documentation/devicetree/bindings/dma/dma.txt.
-
-Example:
-micfil: micfil@30080000 {
- compatible = "fsl,imx8mm-micfil";
- reg = <0x0 0x30080000 0x0 0x10000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_PDM_IPG>,
- <&clk IMX8MM_CLK_PDM_ROOT>;
- clock-names = "ipg_clk", "ipg_clk_app";
- dmas = <&sdma2 24 26 0x80000000>;
-};
diff --git a/Documentation/devicetree/bindings/sound/fsl,micfil.yaml b/Documentation/devicetree/bindings/sound/fsl,micfil.yaml
new file mode 100644
index 000000000000..64d57758ee67
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,micfil.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,micfil.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP MICFIL Digital Audio Interface (MICFIL)
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@xxxxxxx>
+
+description: |
+ The MICFIL digital interface provides a 16-bit or 24-bit audio signal
+ from a PDM microphone bitstream in a configurable output sampling rate.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-micfil
+ - fsl,imx8mp-micfil
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Digital Microphone interface interrupt
+ - description: Digital Microphone interface error interrupt
+ - description: voice activity detector event interrupt
+ - description: voice activity detector error interrupt
+
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for RX
+
+ dma-names:
+ items:
+ - const: rx
+
+ clocks:
+ items:
+ - description: The ipg clock for register access
+ - description: internal micfil clock
+ - description: PLL clock source for 8kHz series
+ - description: PLL clock source for 11kHz series
+ - description: External clock 3
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: ipg_clk
+ - const: ipg_clk_app
+ - const: pll8k
+ - const: pll11k
+ - const: clkext3
+ minItems: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - dmas
+ - dma-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ micfil: audio-controller@30080000 {
+ compatible = "fsl,imx8mm-micfil";
+ reg = <0x30080000 0x10000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PDM_IPG>,
+ <&clk IMX8MM_CLK_PDM_ROOT>;
+ clock-names = "ipg_clk", "ipg_clk_app";
+ dmas = <&sdma2 24 25 0>;
+ dma-names = "rx";
+ };
--
2.17.1