[PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

From: Bharat Kumar Gogada
Date: Tue Jun 21 2022 - 07:37:05 EST


Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
to enable and handle legacy interrupts.

Changes in v5:
- Added of_device_get_match_data to identify CPM version.


Bharat Kumar Gogada (2):
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

.../bindings/pci/xilinx-versal-cpm.yaml | 48 ++++++++++++--
drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++-
2 files changed, 103 insertions(+), 7 deletions(-)

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2.17.1