[atishp04:kvm_isa_ext_v1 1/1] arch/riscv/include/asm/kvm_host.h:173:29: error: 'RISCV_ISA_EXT_MAX' undeclared here (not in a function); did you mean 'KVM_RISCV_ISA_EXT_MAX'?

From: kernel test robot
Date: Thu Jun 16 2022 - 02:26:57 EST


tree: https://github.com/atishp04/linux kvm_isa_ext_v1
head: f581904c5e3c943b3ad5fbaf91606d5f5e12018a
commit: f581904c5e3c943b3ad5fbaf91606d5f5e12018a [1/1] RISC-V: KVM: Improve ISA extension by using a bitmap
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20220616/202206161421.E8pdfIAD-lkp@xxxxxxxxx/config)
compiler: riscv64-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/atishp04/linux/commit/f581904c5e3c943b3ad5fbaf91606d5f5e12018a
git remote add atishp04 https://github.com/atishp04/linux
git fetch --no-tags atishp04 kvm_isa_ext_v1
git checkout f581904c5e3c943b3ad5fbaf91606d5f5e12018a
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=riscv prepare

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

In file included from include/vdso/const.h:5,
from include/linux/const.h:4,
from arch/riscv/include/asm/bug.h:10,
from include/linux/bug.h:5,
from include/linux/mmdebug.h:5,
from include/linux/mm.h:6,
from arch/riscv/kernel/asm-offsets.c:10:
>> arch/riscv/include/asm/kvm_host.h:173:29: error: 'RISCV_ISA_EXT_MAX' undeclared here (not in a function); did you mean 'KVM_RISCV_ISA_EXT_MAX'?
173 | DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
| ^~~~~~~~~~~~~~~~~
include/uapi/linux/const.h:34:40: note: in definition of macro '__KERNEL_DIV_ROUND_UP'
34 | #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
| ^
include/linux/types.h:11:28: note: in expansion of macro 'BITS_TO_LONGS'
11 | unsigned long name[BITS_TO_LONGS(bits)]
| ^~~~~~~~~~~~~
arch/riscv/include/asm/kvm_host.h:173:9: note: in expansion of macro 'DECLARE_BITMAP'
173 | DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
| ^~~~~~~~~~~~~~
make[2]: *** [scripts/Makefile.build:117: arch/riscv/kernel/asm-offsets.s] Error 1
make[2]: Target '__build' not remade because of errors.
make[1]: *** [Makefile:1200: prepare0] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:219: __sub-make] Error 2
make: Target 'prepare' not remade because of errors.


vim +173 arch/riscv/include/asm/kvm_host.h

164
165 struct kvm_vcpu_arch {
166 /* VCPU ran at least once */
167 bool ran_atleast_once;
168
169 /* Last Host CPU on which Guest VCPU exited */
170 int last_exit_cpu;
171
172 /* ISA feature bits (similar to MISA) */
> 173 DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
174
175 /* SSCRATCH, STVEC, and SCOUNTEREN of Host */
176 unsigned long host_sscratch;
177 unsigned long host_stvec;
178 unsigned long host_scounteren;
179
180 /* CPU context of Host */
181 struct kvm_cpu_context host_context;
182
183 /* CPU context of Guest VCPU */
184 struct kvm_cpu_context guest_context;
185
186 /* CPU CSR context of Guest VCPU */
187 struct kvm_vcpu_csr guest_csr;
188
189 /* CPU context upon Guest VCPU reset */
190 struct kvm_cpu_context guest_reset_context;
191
192 /* CPU CSR context upon Guest VCPU reset */
193 struct kvm_vcpu_csr guest_reset_csr;
194
195 /*
196 * VCPU interrupts
197 *
198 * We have a lockless approach for tracking pending VCPU interrupts
199 * implemented using atomic bitops. The irqs_pending bitmap represent
200 * pending interrupts whereas irqs_pending_mask represent bits changed
201 * in irqs_pending. Our approach is modeled around multiple producer
202 * and single consumer problem where the consumer is the VCPU itself.
203 */
204 unsigned long irqs_pending;
205 unsigned long irqs_pending_mask;
206
207 /* VCPU Timer */
208 struct kvm_vcpu_timer timer;
209
210 /* HFENCE request queue */
211 spinlock_t hfence_lock;
212 unsigned long hfence_head;
213 unsigned long hfence_tail;
214 struct kvm_riscv_hfence hfence_queue[KVM_RISCV_VCPU_MAX_HFENCE];
215
216 /* MMIO instruction details */
217 struct kvm_mmio_decode mmio_decode;
218
219 /* SBI context */
220 struct kvm_sbi_context sbi_context;
221
222 /* Cache pages needed to program page tables with spinlock held */
223 struct kvm_mmu_memory_cache mmu_page_cache;
224
225 /* VCPU power-off state */
226 bool power_off;
227
228 /* Don't run the VCPU (blocked) */
229 bool pause;
230 };
231

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