RE: [Intel-wired-lan] [PATCH v2 2/2] igb: Make DMA faster when CPU is active on the PCIe link

[G, GurucharanX]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@xxxxxxxxxx> On Behalf Of
> Kai-Heng Feng
> Sent: Wednesday, May 25, 2022 5:01 PM
> To: Brandeburg, Jesse <jesse.brandeburg@xxxxxxxxx>; Nguyen, Anthony L
> <anthony.l.nguyen@xxxxxxxxx>
> Cc: linux-kernel@xxxxxxxxxxxxxxx; Eric Dumazet <edumazet@xxxxxxxxxx>;
> Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx>; intel-wired-
> lan@xxxxxxxxxxxxxxxx; Jeff Kirsher <jeffrey.t.kirsher@xxxxxxxxx>;
> netdev@xxxxxxxxxxxxxxx; Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo Abeni
> <pabeni@xxxxxxxxxx>; David S. Miller <davem@xxxxxxxxxxxxx>
> Subject: [Intel-wired-lan] [PATCH v2 2/2] igb: Make DMA faster when CPU is
> active on the PCIe link
> 
> Intel I210 on some Intel Alder Lake platforms can only achieve ~750Mbps Tx
> speed via iperf. The RR2DCDELAY shows around 0x2xxx DMA delay, which
> will be significantly lower when 1) ASPM is disabled or 2) SoC package c-state
> stays above PC3. When the RR2DCDELAY is around 0x1xxx the Tx speed can
> reach to ~950Mbps.
> 
> According to the I210 datasheet "8.26.1 PCIe Misc. Register - PCIEMISC",
> "DMA Idle Indication" doesn't seem to tie to DMA coalesce anymore, so set it
> to 1b for "DMA is considered idle when there is no Rx or Tx AND when there
> are no TLPs indicating that CPU is active detected on the PCIe link (such as
> the host executes CSR or Configuration register read or write operation)" and
> performing Tx should also fall under "active CPU on PCIe link" case.
> 
> In addition to that, commit b6e0c419f040 ("igb: Move DMA Coalescing init
> code to separate function.") seems to wrongly changed from enabling
> E1000_PCIEMISC_LX_DECISION to disabling it, also fix that.
> 
> Fixes: b6e0c419f040 ("igb: Move DMA Coalescing init code to separate
> function.")
> Signed-off-by: Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx>
> ---
>  drivers/net/ethernet/intel/igb/igb_main.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 

Tested-by: Gurucharan <gurucharanx.g@xxxxxxxxx> (A Contingent worker at Intel)