Re: [PATCH 3/3] riscv: implement cache-management errata for T-Head SoCs

[Samuel Holland]

On 6/9/22 7:43 PM, Heiko Stuebner wrote:
> The T-Head C906 and C910 implement a scheme for handling
> cache operations different from the generic Zicbom extension.
> 
> Add an errata for it next to the generic dma coherency ops.
> 
> Tested-by: Samuel Holland <samuel@xxxxxxxxxxxx>

v3 breaks Ethernet on D1, because the packet tx buffers are not aligned to the
cache block size. See my comments on patch 2. With the changes suggested there,
all functionality is again working.

Please drop this tag until I have a chance to test the next version.

Regards,
Samuel