Re: [PATCH] gpio: davinci: Add support for system suspend/resume PM

[Bartosz Golaszewski]

On Tue, Jun 7, 2022 at 8:08 AM Aswath Govindraju <a-govindraju@xxxxxx> wrote:
>
> From: Devarsh Thakkar <devarsht@xxxxxx>
>
> Add support for system suspend/resume PM hooks, save the
> register context of all the required gpio registers on suspend
> and restore the context on resume.
>
> Signed-off-by: Devarsh Thakkar <devarsht@xxxxxx>
> Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx>
> ---
>  drivers/gpio/gpio-davinci.c | 84 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 84 insertions(+)
>
> diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
> index f960587f86a3..aca352337c46 100644
> --- a/drivers/gpio/gpio-davinci.c
> +++ b/drivers/gpio/gpio-davinci.c
> @@ -23,6 +23,7 @@
>  #include <linux/irqchip/chained_irq.h>
>  #include <linux/spinlock.h>
>
> +#include <linux/pm_runtime.h>

The below can stay here but please move the pm_runtime include
together with the other linux includes.

>  #include <asm-generic/gpio.h>
>
>  #define MAX_REGS_BANKS 5
> @@ -62,6 +63,8 @@ struct davinci_gpio_controller {
>         void __iomem            *regs[MAX_REGS_BANKS];
>         int                     gpio_unbanked;
>         int                     irqs[MAX_INT_PER_BANK];
> +       struct davinci_gpio_regs context[MAX_REGS_BANKS];
> +       u32                     binten_context;
>  };
>
>  static inline u32 __gpio_mask(unsigned gpio)
> @@ -622,6 +625,86 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
>         return 0;
>  }
>
> +static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
> +                                     u32 nbank)
> +{
> +       struct davinci_gpio_regs __iomem *g = NULL;
> +       struct davinci_gpio_regs *context = NULL;
> +       u32 bank = 0;
> +       void __iomem *base = NULL;

Only initialize variables that need it, please.

> +
> +       base = chips->regs[0] - offset_array[0];
> +       chips->binten_context = readl_relaxed(base + BINTEN);
> +
> +       for (bank = 0; bank < nbank; bank++) {
> +               g = chips->regs[bank];
> +               context = &chips->context[bank];
> +               context->dir = readl_relaxed(&g->dir);
> +               context->set_data = readl_relaxed(&g->set_data);
> +               context->set_rising = readl_relaxed(&g->set_rising);
> +               context->set_falling = readl_relaxed(&g->set_falling);
> +       }
> +
> +       /* Clear Bank interrupt enable bit */
> +       writel_relaxed(0, base + BINTEN);
> +
> +       /* Clear all interrupt status registers */
> +       writel_relaxed(0xFFFFFFFF, &g->intstat);
> +}
> +
> +static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
> +                                        u32 nbank)
> +{
> +       struct davinci_gpio_regs __iomem *g = NULL;
> +       struct davinci_gpio_regs *context = NULL;
> +       u32 bank = 0;
> +       void __iomem *base = NULL;
> +
> +       base = chips->regs[0] - offset_array[0];
> +
> +       if (readl_relaxed(base + BINTEN) != chips->binten_context)
> +               writel_relaxed(chips->binten_context, base + BINTEN);
> +
> +       for (bank = 0; bank < nbank; bank++) {
> +               g = chips->regs[bank];
> +               context = &chips->context[bank];
> +               if (readl_relaxed(&g->dir) != context->dir)
> +                       writel_relaxed(context->dir, &g->dir);
> +               if (readl_relaxed(&g->set_data) != context->set_data)
> +                       writel_relaxed(context->set_data, &g->set_data);
> +               if (readl_relaxed(&g->set_rising) != context->set_rising)
> +                       writel_relaxed(context->set_rising, &g->set_rising);
> +               if (readl_relaxed(&g->set_falling) != context->set_falling)
> +                       writel_relaxed(context->set_falling, &g->set_falling);
> +       }
> +}
> +
> +static int __maybe_unused davinci_gpio_suspend(struct device *dev)
> +{
> +       struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
> +       struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
> +       u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
> +
> +       davinci_gpio_save_context(chips, nbank);
> +
> +       return 0;
> +}
> +
> +static int __maybe_unused davinci_gpio_resume(struct device *dev)
> +{
> +       struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
> +       struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
> +       u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
> +
> +       davinci_gpio_restore_context(chips, nbank);
> +
> +       return 0;
> +}
> +
> +static const struct dev_pm_ops davinci_gpio_dev_pm_ops = {
> +       SET_SYSTEM_SLEEP_PM_OPS(davinci_gpio_suspend, davinci_gpio_resume)
> +};
> +
>  static const struct of_device_id davinci_gpio_ids[] = {
>         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
>         { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
> @@ -634,6 +717,7 @@ static struct platform_driver davinci_gpio_driver = {
>         .probe          = davinci_gpio_probe,
>         .driver         = {
>                 .name           = "davinci_gpio",
> +               .pm = &davinci_gpio_dev_pm_ops,
>                 .of_match_table = of_match_ptr(davinci_gpio_ids),
>         },
>  };
> --
> 2.17.1
>

Bart