switch (msr) {
case MSR_CORE_PERF_FIXED_CTR_CTRL:
case MSR_CORE_PERF_GLOBAL_STATUS:
case MSR_CORE_PERF_GLOBAL_CTRL:
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
- ret = pmu->version > 1;
+ if (host_initiated)
+ return true;
+ return pmu->version > 1;
break;
case MSR_IA32_PEBS_ENABLE:
- ret = perf_capabilities & PERF_CAP_PEBS_FORMAT;
+ if (host_initiated)
+ return true;
+ return perf_capabilities & PERF_CAP_PEBS_FORMAT;
break;
case MSR_IA32_DS_AREA:
- ret = guest_cpuid_has(vcpu, X86_FEATURE_DS);
+ if (host_initiated)
+ return true;
+ return guest_cpuid_has(vcpu, X86_FEATURE_DS);
break;
case MSR_PEBS_DATA_CFG:
- ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) &&
+ if (host_initiated)
+ return true;
+ return (perf_capabilities & PERF_CAP_PEBS_BASELINE) &&
((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3);
break;
default:
- ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
+ if (host_initiated)
+ return true;
+ return get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) ||
intel_pmu_is_valid_lbr_msr(vcpu, msr);
break;
}