Add the exception and interrupt handling machanism for basic LoongArchThis patch mostly looks good, except...
support.
Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
---
arch/loongarch/include/asm/branch.h | 21 +
arch/loongarch/include/asm/bug.h | 23 +
arch/loongarch/include/asm/entry-common.h | 13 +
arch/loongarch/include/asm/hardirq.h | 24 +
arch/loongarch/include/asm/hw_irq.h | 17 +
arch/loongarch/include/asm/irq.h | 130 ++++
arch/loongarch/include/asm/irq_regs.h | 27 +
arch/loongarch/include/asm/irqflags.h | 78 +++
arch/loongarch/include/asm/kdebug.h | 23 +
arch/loongarch/include/asm/stackframe.h | 212 ++++++
arch/loongarch/include/asm/stacktrace.h | 74 +++
arch/loongarch/include/uapi/asm/break.h | 23 +
arch/loongarch/kernel/access-helper.h | 13 +
arch/loongarch/kernel/genex.S | 95 +++
arch/loongarch/kernel/irq.c | 131 ++++
arch/loongarch/kernel/traps.c | 755 ++++++++++++++++++++++
16 files changed, 1659 insertions(+)
create mode 100644 arch/loongarch/include/asm/branch.h
create mode 100644 arch/loongarch/include/asm/bug.h
create mode 100644 arch/loongarch/include/asm/entry-common.h
create mode 100644 arch/loongarch/include/asm/hardirq.h
create mode 100644 arch/loongarch/include/asm/hw_irq.h
create mode 100644 arch/loongarch/include/asm/irq.h
create mode 100644 arch/loongarch/include/asm/irq_regs.h
create mode 100644 arch/loongarch/include/asm/irqflags.h
create mode 100644 arch/loongarch/include/asm/kdebug.h
create mode 100644 arch/loongarch/include/asm/stackframe.h
create mode 100644 arch/loongarch/include/asm/stacktrace.h
create mode 100644 arch/loongarch/include/uapi/asm/break.h
create mode 100644 arch/loongarch/kernel/access-helper.h
create mode 100644 arch/loongarch/kernel/genex.S
create mode 100644 arch/loongarch/kernel/irq.c
create mode 100644 arch/loongarch/kernel/traps.c
(snip)
+asmlinkage void cache_parity_error(void)
+{
+ const int field = 2 * sizeof(unsigned long);
+ unsigned int reg_val;
+
+ /* For the moment, report the problem and hang. */
+ pr_err("Cache error exception:\n");
+ pr_err("csr_merrera == %0*llx\n", field, csr_readq(LOONGARCH_CSR_MERRERA));
+ reg_val = csr_readl(LOONGARCH_CSR_MERRCTL);
+ pr_err("csr_merrctl == %08x\n", reg_val);
+
+ pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
+ reg_val & (1<<30) ? "secondary" : "primary",
+ reg_val & (1<<31) ? "data" : "insn");
+ if (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON)) {
+ pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
+ reg_val & (1<<29) ? "ED " : "",
+ reg_val & (1<<28) ? "ET " : "",
+ reg_val & (1<<27) ? "ES " : "",
+ reg_val & (1<<26) ? "EE " : "",
+ reg_val & (1<<25) ? "EB " : "",
+ reg_val & (1<<24) ? "EI " : "",
+ reg_val & (1<<23) ? "E1 " : "",
+ reg_val & (1<<22) ? "E0 " : "");
+ } else {
+ pr_err("Error bits: %s%s%s%s%s%s%s\n",
+ reg_val & (1<<29) ? "ED " : "",
+ reg_val & (1<<28) ? "ET " : "",
+ reg_val & (1<<26) ? "EE " : "",
+ reg_val & (1<<25) ? "EB " : "",
+ reg_val & (1<<24) ? "EI " : "",
+ reg_val & (1<<23) ? "E1 " : "",
+ reg_val & (1<<22) ? "E0 " : "");
+ }
+ pr_err("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
+
+ panic("Can't handle the cache error!");
+}