Re: [PATCH v6 2/2] watchdog: Add Renesas RZ/N1 Watchdog driver

[Jean-Jacques Hiblot]

On 27/04/2022 15:03, Guenter Roeck wrote:
> On 4/13/22 01:25, Jean-Jacques Hiblot wrote:
> > From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> >
> > This is a driver for the standard WDT on the RZ/N1 devices. This WDT has
> > very limited timeout capabilities. However, it can reset the device.
> > To do so, the corresponding bits in the SysCtrl RSTEN register need to
> > be enabled. This is not done by this driver.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> > Signed-off-by: Jean-Jacques Hiblot <jjhiblot@xxxxxxxxxxxxxxx>
> > Reviewed-by: Tzung-Bi Shih <tzungbi@xxxxxxxxxx>
> > ---
> >   drivers/watchdog/Kconfig    |   8 ++
> >   drivers/watchdog/Makefile   |   1 +
> >   drivers/watchdog/rzn1_wdt.c | 203 ++++++++++++++++++++++++++++++++++++
> >   3 files changed, 212 insertions(+)
> >   create mode 100644 drivers/watchdog/rzn1_wdt.c
> >
> > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> > index c4e82a8d863f..4d5e503c8950 100644
> > --- a/drivers/watchdog/Kconfig
> > +++ b/drivers/watchdog/Kconfig
> > @@ -883,6 +883,14 @@ config RENESAS_RZAWDT
> >         This driver adds watchdog support for the integrated 
> > watchdogs in the
> >         Renesas RZ/A SoCs. These watchdogs can be used to reset a 
> > system.
> >   +config RENESAS_RZN1WDT
> > +    tristate "Renesas RZ/N1 watchdog"
> > +    depends on ARCH_RENESAS || COMPILE_TEST
> > +    select WATCHDOG_CORE
> > +    help
> > +      This driver adds watchdog support for the integrated watchdogs 
> > in the
> > +      Renesas RZ/N1 SoCs. These watchdogs can be used to reset a 
> > system.
> > +
> >   config RENESAS_RZG2LWDT
> >       tristate "Renesas RZ/G2L WDT Watchdog"
> >       depends on ARCH_RENESAS || COMPILE_TEST
> > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> > index f7da867e8782..38d38564f47b 100644
> > --- a/drivers/watchdog/Makefile
> > +++ b/drivers/watchdog/Makefile
> > @@ -84,6 +84,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
> >   obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
> >   obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
> >   obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o
> > +obj-$(CONFIG_RENESAS_RZN1WDT) += rzn1_wdt.o
> >   obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o
> >   obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
> >   obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
> > diff --git a/drivers/watchdog/rzn1_wdt.c b/drivers/watchdog/rzn1_wdt.c
> > new file mode 100644
> > index 000000000000..fa32716727b7
> > --- /dev/null
> > +++ b/drivers/watchdog/rzn1_wdt.c
> > @@ -0,0 +1,203 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Renesas RZ/N1 Watchdog timer.
> > + * This is a 12-bit timer driver from a (62.5/16384) MHz clock. It 
> > can't even
> > + * cope with 2 seconds.
> > + *
> > + * Copyright 2018 Renesas Electronics Europe Ltd.
> > + *
> > + * Derived from Ralink RT288x watchdog timer.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reboot.h>
> > +#include <linux/watchdog.h>
> > +
> > +#define DEFAULT_TIMEOUT        60
> > +
> > +#define RZN1_WDT_RETRIGGER            0x0
> > +#define RZN1_WDT_RETRIGGER_RELOAD_VAL        0
> > +#define RZN1_WDT_RETRIGGER_RELOAD_VAL_MASK    0xfff
> > +#define RZN1_WDT_RETRIGGER_PRESCALE        BIT(12)
> > +#define RZN1_WDT_RETRIGGER_ENABLE        BIT(13)
> > +#define RZN1_WDT_RETRIGGER_WDSI            (0x2 << 14)
> > +
> > +#define RZN1_WDT_PRESCALER            16384
> > +#define RZN1_WDT_MAX                4095
> > +
> > +struct rzn1_watchdog {
> > +    struct watchdog_device        wdtdev;
> > +    void __iomem            *base;
> > +    unsigned long            clk_rate;
>
> Nit: Whenever clk_rate is used, it is divided by 1000.
> It might be better to store and use clk_rate_khz instead.

OK. I'll change this.

Thanks,

JJ

> Guenter