Our CPU arch is just arm64, so I set it to depend on ARM64. Yeah, I never built this for a 32b arch because we would never run this driver on 32b CPU.+F: drivers/perf/hisilicon/hns3_pmu.c
+
HISILICON QM AND ZIP Controller DRIVER
M: Zhou Wang <wangzhou1@xxxxxxxxxxxxx>
L: linux-crypto@xxxxxxxxxxxxxxx
diff --git a/drivers/perf/hisilicon/Kconfig b/drivers/perf/hisilicon/Kconfig
index 5546218b5598..171bfc1b6bc2 100644
--- a/drivers/perf/hisilicon/Kconfig
+++ b/drivers/perf/hisilicon/Kconfig
@@ -14,3 +14,13 @@ config HISI_PCIE_PMU
RCiEP devices.
Adds the PCIe PMU into perf events system for monitoring latency,
bandwidth etc.
+
+config HNS3_PMU
+ tristate "HNS3 PERF PMU"
+ depends on ARM64 || COMPILE_TEST
is see hns3_pmu_readq() below, so you need to ensure the arch supports readq - so I think that you need to depend on 64b. I assume that you never built this for a 32b arch
Are you mean that hns3_pmu_readq() will be compiled failed for 32b arch?