Re: [RFC PATCH v4 0/5] Renesas RZ/G2L IRQC support

[Andy Shevchenko]

On Thu, Mar 17, 2022 at 5:43 AM Lad Prabhakar
<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
>
> Hi All,
>
> The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> Renesas RZ/G2L SoC's with below pins:
> - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
>   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> - NMI edge select.
>
>                                                                 _____________
>                                                                 |    GIC     |
>                                                                 |  ________  |
>                                          ____________           | |        | |
> NMI ------------------------------------>|          |  SPI0-479 | | GIC-600| |
>                 _______                  |          |------------>|        | |
>                 |      |                 |          |  PPI16-31 | |        | |
>                 |      | IRQ0-IRQ7       |   IRQC   |------------>|        | |
> P0_P48_4 ------>| GPIO |---------------->|          |           | |________| |
>                 |      |GPIOINT0-122     |          |           |            |
>                 |      |---------------->| TINT0-31 |           |            |
>                 |______|                 |__________|           |____________|
>
> The proposed RFC patches adds hierarchical IRQ domain one in IRQC driver and other in

add
domain, one
another

> pinctrl driver. Upon interrupt requests map the interrupt to GIC. Out of GPIOINT0-122
> only 32 can be mapped to GIC SPI, this mapping is handled by the pinctrl and IRQC driver.

What I want to know now is whether it is going to collide with Marc's
series about GPIO IRQ chip constification?

-- 
With Best Regards,
Andy Shevchenko