Re: [PATCH v2 7/7] clk: qcom: Add SDX65 APCS clock controller support

[Stephen Boyd]

Quoting Rohit Agarwal (2022-02-15 02:09:13)
> Add a driver config support for the SDX65 APCS clock controller. It is part

Maybe "Add a driver config" is a little strong for the patch contents.
More like "Update APCS Kconfig to reflect support for another SoC".

> of the APCS hardware block, which among other things implements a combined
> mux and half integer divider functionality. The APCS clock controller has 3
> parent clocks:
> 
> 1. Board XO
> 2. Fixed rate GPLL0
> 3. A7 PLL
> 
> This is required for enabling CPU frequency scaling on SDX65-based
> platforms.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx>