Re: [PATCH v2 2/2] clk: qcom: Add MSM8226 Multimedia Clock Controller support

[Stephen Boyd]

Quoting Bartosz Dudziak (2022-02-07 10:54:11)
> Modify the existing MSM8974 multimedia clock controller driver to
> support the MMCC found on MSM8226 based devices. This should allow most
> multimedia device drivers to probe and control their clocks.
> 
> Signed-off-by: Bartosz Dudziak <bartosz.dudziak@xxxxxxxx>
> ---
>  drivers/clk/qcom/mmcc-msm8974.c | 206 +++++++++++++++++++++++++++++++-
>  1 file changed, 201 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index a1552b6771..f74662925a 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -257,6 +257,18 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
>         },
>  };
>  
> +static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {

const?

> +       F(19200000, P_XO, 1, 0, 0),
> +       F(37500000, P_GPLL0, 16, 0, 0),
> +       F(50000000, P_GPLL0, 12, 0, 0),
> +       F(75000000, P_GPLL0, 8, 0, 0),
> +       F(100000000, P_GPLL0, 6, 0, 0),
> +       F(150000000, P_GPLL0, 4, 0, 0),
> +       F(200000000, P_MMPLL0, 4, 0, 0),
> +       F(266666666, P_MMPLL0, 3, 0, 0),
> +       { }
> +};
> +
>  static struct freq_tbl ftbl_mmss_axi_clk[] = {
>         F( 19200000, P_XO, 1, 0, 0),
>         F( 37500000, P_GPLL0, 16, 0, 0),
> @@ -364,6 +376,23 @@ static struct clk_rcg2 csi3_clk_src = {
>         },
>  };
>  
> +static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {

const?

> +       F(37500000, P_GPLL0, 16, 0, 0),
> +       F(50000000, P_GPLL0, 12, 0, 0),
> +       F(60000000, P_GPLL0, 10, 0, 0),
> +       F(80000000, P_GPLL0, 7.5, 0, 0),
> +       F(100000000, P_GPLL0, 6, 0, 0),
> +       F(109090000, P_GPLL0, 5.5, 0, 0),
> +       F(133330000, P_GPLL0, 4.5, 0, 0),
> +       F(150000000, P_GPLL0, 4, 0, 0),
> +       F(200000000, P_GPLL0, 3, 0, 0),
> +       F(228570000, P_MMPLL0, 3.5, 0, 0),
> +       F(266670000, P_MMPLL0, 3, 0, 0),
> +       F(320000000, P_MMPLL0, 2.5, 0, 0),
> +       F(400000000, P_MMPLL0, 2, 0, 0),
> +       { }
> +};
> +
>  static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
>         F(37500000, P_GPLL0, 16, 0, 0),
>         F(50000000, P_GPLL0, 12, 0, 0),
> @@ -407,6 +436,18 @@ static struct clk_rcg2 vfe1_clk_src = {
>         },
>  };
>  
> +static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {

const?

> +       F(37500000, P_GPLL0, 16, 0, 0),
> +       F(60000000, P_GPLL0, 10, 0, 0),
> +       F(75000000, P_GPLL0, 8, 0, 0),
> +       F(92310000, P_GPLL0, 6.5, 0, 0),
> +       F(100000000, P_GPLL0, 6, 0, 0),
> +       F(133330000, P_MMPLL0, 6, 0, 0),
> +       F(177780000, P_MMPLL0, 4.5, 0, 0),
> +       F(200000000, P_MMPLL0, 4, 0, 0),
> +       { }
> +};
> +
>  static struct freq_tbl ftbl_mdss_mdp_clk[] = {
>         F(37500000, P_GPLL0, 16, 0, 0),
>         F(60000000, P_GPLL0, 10, 0, 0),
> @@ -513,6 +554,14 @@ static struct clk_rcg2 pclk1_clk_src = {
>         },
>  };
>  
> +static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {

const?

> +       F(66700000, P_GPLL0, 9, 0, 0),
> +       F(100000000, P_GPLL0, 6, 0, 0),
> +       F(133330000, P_MMPLL0, 6, 0, 0),
> +       F(160000000, P_MMPLL0, 5, 0, 0),
> +       { }
> +};
> +
>  static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
>         F(50000000, P_GPLL0, 12, 0, 0),
>         F(100000000, P_GPLL0, 6, 0, 0),
> @@ -593,6 +642,13 @@ static struct clk_rcg2 camss_gp1_clk_src = {
>         },
>  };
>  
> +static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {

const?

> +       F(19200000, P_XO, 1, 0, 0),
> +       F(24000000, P_GPLL0, 5, 1, 5),
> +       F(66670000, P_GPLL0, 9, 0, 0),
> +       { }
> +};
> +
>  static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
>         F(4800000, P_XO, 4, 0, 0),
>         F(6000000, P_GPLL0, 10, 1, 10),
> @@ -705,6 +761,15 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
>         },
>  };
>  
> +static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {

const?

> +       F(133330000, P_GPLL0, 4.5, 0, 0),
> +       F(150000000, P_GPLL0, 4, 0, 0),
> +       F(266670000, P_MMPLL0, 3, 0, 0),
> +       F(320000000, P_MMPLL0, 2.5, 0, 0),
> +       F(400000000, P_MMPLL0, 2, 0, 0),
> +       { }
> +};
> +