Re: [PATCH] spi: disable chipselect after complete transfer

[Mark Brown]

On Wed, Feb 09, 2022 at 06:00:42PM +0800, Yun Zhou wrote:
> If there are 2 slaves or more on a spi bus, e.g. A and B, we processed a
> transfer to A, the CS will be selected for A whose 'last_cs_enable' will
> be recorded to true at the same time. Then we processed a transfer to B,
> the CS will be switched to B. And then if we transmit data to A again, it
> will not enable CS back to A because 'last_cs_enable' is true.
> In addition, if CS is not disabled, Some controllers in automatic
> transmission state will receive unpredictable data, such as Cadence SPI
> controller.

This sounds like you've got an issue with mixing devices with and
without CS_HIGH - that is probably broken but...

>  out:
> -	if (ret != 0 || !keep_cs)
> -		spi_set_cs(msg->spi, false, false);
> +	spi_set_cs(msg->spi, false, false);

...this will obviously break cs_change support, clearly that's not OK.
The last_cs_high should be moved to the device.

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