[PATCH] usb: xhci: refactor quirks and plat private data

From: Pavankumar Kondeti
Date: Wed Feb 09 2022 - 00:44:08 EST

Next message: Ira Weiny: "Re: [PATCH V8 06/44] mm/pkeys: Add Kconfig options for PKS"
Previous message: Amit Kumar Mahapatra: "[PATCH v2] mtd: rawnand: pl353: Set the nand chip node as the flash node"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This refactoring allows drivers like dwc3 host glue driver to
specify thier xhci quirks.

Change-Id: Ia9f6347c3e752d8f75bdeafb914d335629a26900
Signed-off-by: Pavankumar Kondeti <quic_pkondeti@xxxxxxxxxxx>
---
drivers/usb/cdns3/host.c | 2 +-
drivers/usb/host/xhci-plat.c | 3 +-
drivers/usb/host/xhci-rcar.c | 3 +-
drivers/usb/host/xhci.h | 60 ++-----------------
.../usb/host => include/linux/usb}/xhci-plat.h | 5 +-
include/linux/usb/xhci-quirks.h | 67 ++++++++++++++++++++++
6 files changed, 80 insertions(+), 60 deletions(-)
rename {drivers/usb/host => include/linux/usb}/xhci-plat.h (74%)
create mode 100644 include/linux/usb/xhci-quirks.h

diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c
index 84dadfa..02634d9 100644
--- a/drivers/usb/cdns3/host.c
+++ b/drivers/usb/cdns3/host.c
@@ -14,8 +14,8 @@
#include "drd.h"
#include "host-export.h"
#include <linux/usb/hcd.h>
+#include <linux/usb/xhci-plat.h>
#include "../host/xhci.h"
-#include "../host/xhci-plat.h"

#define XECP_PORT_CAP_REG 0x8000
#define XECP_AUX_CTRL_REG1 0x8120
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index c1edcc9..23e0de0 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -19,9 +19,10 @@
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/usb/of.h>
+#include <linux/usb/xhci-quirks.h>
+#include <linux/usb/xhci-plat.h>

#include "xhci.h"
-#include "xhci-plat.h"
#include "xhci-mvebu.h"
#include "xhci-rcar.h"

diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index 9888ba7..cbcb6ba 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -12,9 +12,10 @@
#include <linux/of.h>
#include <linux/usb/phy.h>
#include <linux/sys_soc.h>
+#include <linux/usb/xhci-quirks.h>
+#include <linux/usb/xhci-plat.h>

#include "xhci.h"
-#include "xhci-plat.h"
#include "xhci-rcar.h"

/*
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 5a75fe5..4e80d08 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -17,6 +17,8 @@
#include <linux/kernel.h>
#include <linux/usb/hcd.h>
#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/usb/xhci-quirks.h>
+#include <linux/usb/xhci-plat.h>

/* Code sharing between pci-quirks and xhci hcd */
#include "xhci-ext-caps.h"
@@ -1846,60 +1848,6 @@ struct xhci_hcd {
#define XHCI_STATE_HALTED (1 << 1)
#define XHCI_STATE_REMOVING (1 << 2)
unsigned long long quirks;
-#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
-#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
-#define XHCI_NEC_HOST BIT_ULL(2)
-#define XHCI_AMD_PLL_FIX BIT_ULL(3)
-#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
-/*
- * Certain Intel host controllers have a limit to the number of endpoint
- * contexts they can handle. Ideally, they would signal that they can't handle
- * anymore endpoint contexts by returning a Resource Error for the Configure
- * Endpoint command, but they don't. Instead they expect software to keep track
- * of the number of active endpoints for them, across configure endpoint
- * commands, reset device commands, disable slot commands, and address device
- * commands.
- */
-#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
-#define XHCI_BROKEN_MSI BIT_ULL(6)
-#define XHCI_RESET_ON_RESUME BIT_ULL(7)
-#define XHCI_SW_BW_CHECKING BIT_ULL(8)
-#define XHCI_AMD_0x96_HOST BIT_ULL(9)
-#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
-#define XHCI_LPM_SUPPORT BIT_ULL(11)
-#define XHCI_INTEL_HOST BIT_ULL(12)
-#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
-#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
-#define XHCI_AVOID_BEI BIT_ULL(15)
-#define XHCI_PLAT BIT_ULL(16)
-#define XHCI_SLOW_SUSPEND BIT_ULL(17)
-#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
-/* For controllers with a broken beyond repair streams implementation */
-#define XHCI_BROKEN_STREAMS BIT_ULL(19)
-#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
-#define XHCI_MTK_HOST BIT_ULL(21)
-#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
-#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
-#define XHCI_MISSING_CAS BIT_ULL(24)
-/* For controller with a broken Port Disable implementation */
-#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
-#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
-#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
-#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
-#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
-#define XHCI_SUSPEND_DELAY BIT_ULL(30)
-#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
-#define XHCI_ZERO_64B_REGS BIT_ULL(32)
-#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
-#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
-#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
-#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
-#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
-#define XHCI_DISABLE_SPARSE BIT_ULL(38)
-#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
-#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
-#define XHCI_BROKEN_D3COLD BIT_ULL(41)
-#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)

unsigned int num_active_eps;
unsigned int limit_active_eps;
@@ -1965,6 +1913,10 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
return xhci->main_hcd;
}

+/* For xhci-plat drivers */
+#define hcd_to_xhci_priv(h) ((struct xhci_plat_priv *)hcd_to_xhci(h)->priv)
+#define xhci_to_priv(x) ((struct xhci_plat_priv *)(x)->priv)
+
#define xhci_dbg(xhci, fmt, args...) \
dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
#define xhci_err(xhci, fmt, args...) \
diff --git a/drivers/usb/host/xhci-plat.h b/include/linux/usb/xhci-plat.h
similarity index 74%
rename from drivers/usb/host/xhci-plat.h
rename to include/linux/usb/xhci-plat.h
index 561d0b7..0612258 100644
--- a/drivers/usb/host/xhci-plat.h
+++ b/include/linux/usb/xhci-plat.h
@@ -8,7 +8,8 @@
#ifndef _XHCI_PLAT_H
#define _XHCI_PLAT_H

-#include "xhci.h" /* for hcd_to_xhci() */
+#include <linux/types.h>
+#include <linux/usb/hcd.h>

struct xhci_plat_priv {
const char *firmware_name;
@@ -20,6 +21,4 @@ struct xhci_plat_priv {
int (*resume_quirk)(struct usb_hcd *);
};

-#define hcd_to_xhci_priv(h) ((struct xhci_plat_priv *)hcd_to_xhci(h)->priv)
-#define xhci_to_priv(x) ((struct xhci_plat_priv *)(x)->priv)
#endif /* _XHCI_PLAT_H */
diff --git a/include/linux/usb/xhci-quirks.h b/include/linux/usb/xhci-quirks.h
new file mode 100644
index 00000000..57ae0b1
--- /dev/null
+++ b/include/linux/usb/xhci-quirks.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * xHCI host controller driver quirks
+ *
+ * Copyright (C) 2008 Intel Corp.
+ */
+
+#ifndef _XHCI_QUIRKS_H
+#define _XHCI_QUIRKS_H
+
+#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
+#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
+#define XHCI_NEC_HOST BIT_ULL(2)
+#define XHCI_AMD_PLL_FIX BIT_ULL(3)
+#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
+/*
+ * Certain Intel host controllers have a limit to the number of endpoint
+ * contexts they can handle. Ideally, they would signal that they can't handle
+ * anymore endpoint contexts by returning a Resource Error for the Configure
+ * Endpoint command, but they don't. Instead they expect software to keep track
+ * of the number of active endpoints for them, across configure endpoint
+ * commands, reset device commands, disable slot commands, and address device
+ * commands.
+ */
+#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
+#define XHCI_BROKEN_MSI BIT_ULL(6)
+#define XHCI_RESET_ON_RESUME BIT_ULL(7)
+#define XHCI_SW_BW_CHECKING BIT_ULL(8)
+#define XHCI_AMD_0x96_HOST BIT_ULL(9)
+#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
+#define XHCI_LPM_SUPPORT BIT_ULL(11)
+#define XHCI_INTEL_HOST BIT_ULL(12)
+#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
+#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
+#define XHCI_AVOID_BEI BIT_ULL(15)
+#define XHCI_PLAT BIT_ULL(16)
+#define XHCI_SLOW_SUSPEND BIT_ULL(17)
+#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
+/* For controllers with a broken beyond repair streams implementation */
+#define XHCI_BROKEN_STREAMS BIT_ULL(19)
+#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
+#define XHCI_MTK_HOST BIT_ULL(21)
+#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
+#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
+#define XHCI_MISSING_CAS BIT_ULL(24)
+/* For controller with a broken Port Disable implementation */
+#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
+#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
+#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
+#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
+#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
+#define XHCI_SUSPEND_DELAY BIT_ULL(30)
+#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
+#define XHCI_ZERO_64B_REGS BIT_ULL(32)
+#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
+#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
+#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
+#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
+#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
+#define XHCI_DISABLE_SPARSE BIT_ULL(38)
+#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
+#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
+#define XHCI_BROKEN_D3COLD BIT_ULL(41)
+#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
+
+#endif /* _XHCI_QUIRKS_H */
--
2.7.4

--zYM0uCDKw75PZbzx--

Next message: Ira Weiny: "Re: [PATCH V8 06/44] mm/pkeys: Add Kconfig options for PKS"
Previous message: Amit Kumar Mahapatra: "[PATCH v2] mtd: rawnand: pl353: Set the nand chip node as the flash node"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]