Re: [PATCH v2 2/2] PCI: designware-ep: Fix the access to DBI/iATU registers before enabling controller

[Kunihiko Hayashi]

Hi Kishon, Lorenzo,

Thank you and sorry for late reply.

On 2021/12/06 20:23, Lorenzo Pieralisi wrote:
> On Fri, Dec 03, 2021 at 10:36:00AM +0530, Kishon Vijay Abraham I wrote:
> > Hi Kunihiko,
> >
> > On 01/09/21 10:46 am, Kunihiko Hayashi wrote:
> > > The driver using core_init_notifier, e.g. pcie-tegra194.c, runs
> according
> > > to the following sequence:
> > >
> > >      probe()
> > >          dw_pcie_ep_init()
> > >
> > >      bind()
> > >          dw_pcie_ep_start()
> > >              enable_irq()
> > >
> > >      (interrupt occurred)
> > >      handler()
> > >          [enable controller]
> > >          dw_pcie_ep_init_complete()
> > >          dw_pcie_ep_init_notify()
> > >
> > > After receiving an interrupt from RC, the handler enables the
> controller
> > > and the controller registers can be accessed.
> > > So accessing the registers should do in dw_pcie_ep_init_complete().
> > >
> > > Currently dw_pcie_ep_init() has functions dw_iatu_detect() and
> > > dw_pcie_ep_find_capability() that include accesses to DWC registers.
> > > As a result, accessing the registers before enabling the controller,
> > > the access will fail.
> > >
> > > The function dw_pcie_ep_init() shouldn't have any access to DWC
> registers
> > > if the controller is enabled after calling bind(). This moves access
> codes
> > > to DBI/iATU registers and depending variables from dw_pcie_ep_init()
> to
> > > dw_pcie_ep_init_complete().
> >
> > Ideally pci_epc_create() should be the last step by the controller
> > driver before handing the control to the core EPC framework. Since
> > after this step the EPC framework can start invoking the epc_ops.
> >
> > Here more stuff is being added to dw_pcie_ep_init_complete() which is
> > required for epc_ops and this could result in aborts for platforms
> > which does not add core_init_notifier.
>
> This patch needs rework, I will mark the series as "Changes requested".

I understand that relocation of dwc register accesses isn't appropriate,
but I couldn't think of any other rework to dwc, and I confirmed
pcie-qcom-ep driver using core_init_notifier.

In pcie-qcom-ep driver, probe() enables clock and deasserts reset first,
and when PERST# interrupt arrives, the handler enables clock and deasserts
reset again. So, dw_pcie_ep_init() can access DBI registers.

In pcie-tegra194 driver, I think the issue will be solved if probe() also
handles clock and reset control. However, the driver has other register
access between core_clk, core_apb_rst, and core_rst controls.
I think that it's appropriate to leave this fix to the developer at this
point.

As this patch series, I'll resend 1/2 patch only and expect pcie-tegra194
driver to be fixed.

Thank you,

---
Best Regards
Kunihiko Hayashi