[irqchip: irq/irqchip-next] irqchip/spear-shirq: Add support for IRQ 0..6

[irqchip-bot for Herve Codina]

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     f63c862587c9ba1c62de8c549e8f2fbe0fc88b6b
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/f63c862587c9ba1c62de8c549e8f2fbe0fc88b6b
Author:        Herve Codina <herve.codina@xxxxxxxxxxx>
AuthorDate:    Thu, 02 Dec 2021 10:52:54 +01:00
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Thu, 16 Dec 2021 13:29:44 

irqchip/spear-shirq: Add support for IRQ 0..6

IRQ 0..7 are not supported by the driver for SPEAr320 SOC family.

IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT).
Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned
as follow:
  IRQ 6 - NGPIO_INTR: Combined status of edge programmable
                      interrupts from GPIO ports
  IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun
  IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty
  IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun
  IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO
  IRQ 1 - Reserved
  IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports

Add support for these IRQs in SPEAr320 SOC family.

Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx>
Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
Acked-by: Arnd Bergmann <arnd@xxxxxxxx>
Acked-by: Viresh Kumar <viresh.kumar@xxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20211202095255.165797-6-herve.codina@xxxxxxxxxxx
---
 drivers/irqchip/spear-shirq.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
index 1518ba3..7c17a6f 100644
--- a/drivers/irqchip/spear-shirq.c
+++ b/drivers/irqchip/spear-shirq.c
@@ -149,6 +149,8 @@ static struct spear_shirq spear320_shirq_ras3 = {
 	.offset		= 0,
 	.nr_irqs	= 7,
 	.mask		= ((0x1 << 7) - 1) << 0,
+	.irq_chip	= &dummy_irq_chip,
+	.status_reg	= SPEAR320_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq spear320_shirq_ras1 = {