Re: [PATCH] i2c: tegra: use i2c_timings for bus clock freq

[Andy Shevchenko]

On Thu, Dec 9, 2021 at 3:48 PM Akhil R <akhilrajeev@xxxxxxxxxx> wrote:
>
> Use i2c_timings struct and corresponding methods to get bus clock frequency

Thanks!
A couple of comments below, after addressing them, FWIW,
Reviewed-by: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>

> Signed-off-by: Akhil R <akhilrajeev@xxxxxxxxxx>
> ---
>  drivers/i2c/busses/i2c-tegra.c | 19 ++++++++-----------
>  1 file changed, 8 insertions(+), 11 deletions(-)
>
> The patch is in response to the discussion in a previous patch to use
> i2c_timings struct for bus freq.
> ref. https://lkml.org/lkml/2021/11/25/767

A-ha.
Suggested-by: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
(or @linux.intel.com, I can't see it there)

> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index a5be8f0..ffd2ad2 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -246,7 +246,7 @@ struct tegra_i2c_hw_feature {
>   * @msg_buf: pointer to current message data
>   * @msg_buf_remaining: size of unsent data in the message buffer
>   * @msg_read: indicates that the transfer is a read access
> - * @bus_clk_rate: current I2C bus clock rate
> + * @timings: i2c timings information like bus frequency
>   * @multimaster_mode: indicates that I2C controller is in multi-master mode
>   * @tx_dma_chan: DMA transmit channel
>   * @rx_dma_chan: DMA receive channel
> @@ -273,7 +273,7 @@ struct tegra_i2c_dev {
>         unsigned int nclocks;
>
>         struct clk *div_clk;
> -       u32 bus_clk_rate;
> +       struct i2c_timings timings;
>
>         struct completion msg_complete;
>         size_t msg_buf_remaining;
> @@ -642,14 +642,14 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
>         if (i2c_dev->is_vi)
>                 tegra_i2c_vi_init(i2c_dev);
>
> -       switch (i2c_dev->bus_clk_rate) {
> +       switch (i2c_dev->timings.bus_freq_hz) {

It would be easier to have all these to read when you introduce a
temporary variable:

  struct i2c_timings *t = &i2c_dev->timings;
  ...
  switch (t->...) {
  ...

>         case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
>         default:
>                 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
>                 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
>                 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
>
> -               if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
> +               if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
>                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
>                 else
>                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
> @@ -685,7 +685,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
>         clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
>
>         err = clk_set_rate(i2c_dev->div_clk,
> -                          i2c_dev->bus_clk_rate * clk_multiplier);
> +                          i2c_dev->timings.bus_freq_hz * clk_multiplier);
>         if (err) {
>                 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
>                 return err;
> @@ -724,7 +724,7 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
>          * before disabling the controller so that the STOP condition has
>          * been delivered properly.
>          */
> -       udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
> +       udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
>
>         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
>         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
> @@ -1254,7 +1254,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
>          * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
>          */
>         xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
> -                                      i2c_dev->bus_clk_rate);
> +                                      i2c_dev->timings.bus_freq_hz);
>
>         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
>         tegra_i2c_unmask_irq(i2c_dev, int_mask);
> @@ -1633,10 +1633,7 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
>         bool multi_mode;
>         int err;
>
> -       err = device_property_read_u32(i2c_dev->dev, "clock-frequency",
> -                                      &i2c_dev->bus_clk_rate);
> -       if (err)
> -               i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
> +       i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
>
>         multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
>         i2c_dev->multimaster_mode = multi_mode;
> --
> 2.7.4
>


-- 
With Best Regards,
Andy Shevchenko