Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures

[Will Deacon]

On Tue, Oct 19, 2021 at 12:36:48PM +0100, Suzuki K Poulose wrote:
> On 19/10/2021 12:02, Will Deacon wrote:
> > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote:
> > > @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> > >   		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> > >   		CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
> > >   	},
> > > +#endif
> > > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE
> > 
> > You still haven't fixed this typo...
> > 
> 
> Sorry about that. I thought it was about selecting the
> Kconfig entries, which was fixed. I will fix this.

Sorry, I thought it was such a howler that it would've jumped out ;)
That's what made me think we should make sure the series compiles without
the coresight changes, so we can catch these problems early.

> > Seriously, I get compile warnings from this -- are you not seeing them?
> 
> No, I don't get any warnings. Is there something that I am missing ?

Interesting. I see the warning below in my bisection testing, since the typo
means that the midr lookup table isn't used. Maybe you're only compiling the
end result?

Will

--->8

+arch/arm64/kernel/cpu_errata.c:356:32: warning: ‘tsb_flush_fail_cpus’ defined but not used [-Wunused-const-variable=]
+  356 | static const struct midr_range tsb_flush_fail_cpus[] = {
+      |                                ^~~~~~~~~~~~~~~~~~~