Re: [PATCH] EDAC/amd64: Handle three rank interleaving mode

[Borislav Petkov]

On Tue, Oct 05, 2021 at 03:44:19PM +0000, Yazen Ghannam wrote:
> AMD Rome systems and later support interleaving between three identical
> ranks within a channel.
> 
> Check for this mode by counting the number of enabled chip selects and
> comparing their masks. If there are exactly three enabled chip selects
> and their masks are identical, then three rank interleaving is enabled.
> 
> The size of a rank is determined from its mask value. However, three
> rank interleaving doesn't follow the method of swapping an interleave
> bit with the most significant bit. Rather, the interleave bit is flipped
> and the most significant bit remains the same. There is only a single
> interleave bit in this case.
> 
> Account for this when determining the chip select size by keeping the
> most significant bit at its original value and ignoring any zero bits.
> This will return a full bitmask in [MSB:1].
> 
> Fixes: e53a3b267fb0 ("EDAC/amd64: Find Chip Select memory size using Address Mask")
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@xxxxxxx>
> ---
>  drivers/edac/amd64_edac.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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