Re: [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode

[Apurva Nandan]

Hi Miquèl,

On 07/08/21 12:13 am, Miquel Raynal wrote:
> Hi Apurva,
>
> Apurva Nandan <a-nandan@xxxxxx> wrote on Tue, 13 Jul 2021 13:05:29
> +0000:
>
> > In Octal DTR SPI mode, 2 bytes of data gets transmitted over one clock
> > cycle, and half-cycle instruction phases aren't supported yet. So,
> > every DTR spi_mem_op needs to have even nbytes in all phases for
> > non-erratic behaviour from the SPI controller.
> >
> > The odd length cmd and dummy phases get handled by spimem_setup_op()
> > but the odd length address and data phases need to be handled according
> > to the use case. For example in Octal DTR mode, read register operation
> > has one byte long address and data phase. So it needs to extend it
> > by adding a suitable extra byte in addr and reading 2 bytes of data,
> > discarding the second byte.
> >
> > Handle address and data phases for Octal DTR mode in read/write
> > register and write volatile configuration register operations
> > by adding a suitable extra byte in the address and data phase.
> >
> > Create spimem_setup_reg_op() helper function to ease setting up
> > read/write register operations in other functions, e.g. wait().
> >
> > Signed-off-by: Apurva Nandan <a-nandan@xxxxxx>
> > ---
> >   drivers/mtd/nand/spi/core.c | 26 +++++++++++++++++++++-----
> >   1 file changed, 21 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> > index 2e59faecc8f5..a5334ad34f96 100644
> > --- a/drivers/mtd/nand/spi/core.c
> > +++ b/drivers/mtd/nand/spi/core.c
> > @@ -65,12 +65,27 @@ static void spinand_setup_op(const struct spinand_device *spinand,
> >   	}
> >   }
> >   
> > +static void spinand_setup_reg_op(const struct spinand_device *spinand,
> > +				 struct spi_mem_op *op)
>
> Same remark about the naming. In fact I believe we could have this
> logic in _setup_op() (or whatever its name) and add a specific
> parameter for it?

Okay, I will add a parameter in argument and include this logic in 
_setup_op().

> > +{
> > +	if (spinand->reg_proto == SPINAND_OCTAL_DTR) {
> > +		/*
> > +		 * Assigning same first and second byte will result in constant
> > +		 * bits on ths SPI bus between positive and negative clock edges
>
>                             the

Ok.

> > +		 */
> > +		op->addr.val = (op->addr.val << 8) | op->addr.val;
>
> I am not sure to understand what you do here?

In Octal DTR mode, 2 bytes of data are sent in a clock cycle. So, we 
need to append one extra byte when sending a single byte. This extra 
byte would be sent on the negative edge.

It will make sense to keep both the bytes same, as when it will be set 
on the SPI pins, the bits on the SPI IO ports will remain constant 
between the positive and negative edges (as 1 complete byte is set in 
one clock edge in MSB order). There are no restrictions by the 
manufacturers on this, the relevant address byte needs to be on positive 
edge and second byte on negative edge is don't care.

> > +		op->addr.nbytes = 2;
> > +		op->data.nbytes = 2;
> > +	}
>
> Space

Ok.

> > +	spinand_setup_op(spinand, op);
> > +}
> > +
> >   static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
> >   {
> > -	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
> > -						      spinand->scratchbuf);
> > +	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, spinand->scratchbuf);
>
> You can do this, but in a different commit.

Got it.

> >   	int ret;
> >   
> > +	spinand_setup_reg_op(spinand, &op);
> >   	ret = spi_mem_exec_op(spinand->spimem, &op);
> >   	if (ret)
> >   		return ret;
> > @@ -81,10 +96,10 @@ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
> >   
> >   static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
> >   {
> > -	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
> > -						      spinand->scratchbuf);
> > +	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, spinand->scratchbuf);
>
> Same here.

Yes!

> >   
> > -	*spinand->scratchbuf = val;
> > +	spinand_setup_reg_op(spinand, &op);
> > +	memset(spinand->scratchbuf, val, op.data.nbytes);
> >   	return spi_mem_exec_op(spinand->spimem, &op);
> >   }
> >   
> > @@ -547,6 +562,7 @@ static int spinand_wait(struct spinand_device *spinand,
> >   	u8 status;
> >   	int ret;
> >   
> > +	spinand_setup_reg_op(spinand, &op);
> >   	ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0,
> >   				  initial_delay_us,
> >   				  poll_delay_us,
>
> Thanks,
> Miquèl
>
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Thanks,
Apurva Nandan