Re: [PATCH v12] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY

[kernel test robot]

Hi Mauro,

I love your patch! Yet something to improve:

[auto build test ERROR on linus/master]
[also build test ERROR on v5.14-rc6 next-20210818]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/phy-HiSilicon-Add-driver-for-Kirin-970-PCIe-PHY/20210818-190539
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 614cb2751d3150850d459bee596c397f344a7936
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/90e806228f10f8375d808f4813c6ea64aaa91a2a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Mauro-Carvalho-Chehab/phy-HiSilicon-Add-driver-for-Kirin-970-PCIe-PHY/20210818-190539
        git checkout 90e806228f10f8375d808f4813c6ea64aaa91a2a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=ia64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

   drivers/phy/hisilicon/phy-hi3670-pcie.c: In function 'hi3670_pcie_set_eyeparam':
>> drivers/phy/hisilicon/phy-hi3670-pcie.c:257:24: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
     257 |                 val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
         |                        ^~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/FIELD_PREP +257 drivers/phy/hisilicon/phy-hi3670-pcie.c

   248	
   249	static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
   250	{
   251		u32 val;
   252	
   253		val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
   254	
   255		if (phy->eye_param[1] != EYEPARAM_NOCFG) {
   256			val &= ~EYE_PARM1_MASK;
 > 257			val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
   258			val |= EYE_PARM1_EN;
   259		}
   260		kirin_apb_natural_phy_writel(phy, val,
   261					     RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
   262	
   263		val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
   264		val &= ~(EYE_PARM2_MASK | EYE_PARM3_MASK);
   265		if (phy->eye_param[2] != EYEPARAM_NOCFG) {
   266			val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
   267			val |= EYE_PARM2_EN;
   268		}
   269	
   270		if (phy->eye_param[3] != EYEPARAM_NOCFG) {
   271			val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
   272			val |= EYE_PARM3_EN;
   273		}
   274	
   275		kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
   276	
   277		val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
   278		if (phy->eye_param[0] != EYEPARAM_NOCFG) {
   279			val &= ~EYE_PARM0_MASK;
   280			val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
   281			val |= EYE_PARM0_EN;
   282		}
   283		kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
   284	
   285		val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
   286		if (phy->eye_param[4] != EYEPARAM_NOCFG) {
   287			val &= ~EYE_PARM4_MASK;
   288			val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
   289			val |= EYE_PARM4_EN;
   290		}
   291		kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
   292	}
   293	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

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