[PATCH v13 5/6] arm64: dts: rockchip: Add SFC to RK3308

From: Jon Lin
Date: Thu Aug 12 2021 - 09:46:56 EST


From: Chris Morgan <macromorgan@xxxxxxxxxxx>

Add a devicetree entry for the Rockchip SFC for the RK3308 SOC.

Signed-off-by: Chris Morgan <macromorgan@xxxxxxxxxxx>
Signed-off-by: Jon Lin <jon.lin@xxxxxxxxxxxxxx>
---

Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None

arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index a185901aba9a..ce6f4a28d169 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -731,6 +731,17 @@
status = "disabled";
};

+ sfc: spi@ff4c0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff4c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
@@ -1004,6 +1015,32 @@
};
};

+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ <3 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <3 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
gmac {
rmii_pins: rmii-pins {
rockchip,pins =
--
2.17.1