Re: [RESEND PATCH] perf/x86/intel/uncore: Support extra IMC channel on Ice Lake server

[Liang, Kan]

Hi Peter,

Could you please pick up the fix?
Please let me know if you have any comments/concerns.

Thanks,
Kan

On 7/19/2021 8:54 AM, kan.liang@xxxxxxxxxxxxxxx wrote:
> From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
>
> There are three channels on a Ice Lake server, but only two channels
> will ever be active. Current perf only enables two channels.
>
> Support the extra IMC channel, which may be activated on some Ice Lake
> machines. For a non-activated channel, the SW can still access it. The
> write will be ignored by the HW. 0 is always returned for the reading.
>
> Fixes: 2b3b76b5ec67 ("perf/x86/intel/uncore: Add Ice Lake server uncore support")
> Reviewed-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
> ---
>
>   arch/x86/events/intel/uncore_snbep.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index 9a178a9..72a4181 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -452,7 +452,7 @@
>   #define ICX_M3UPI_PCI_PMON_BOX_CTL		0xa0
>   
>   /* ICX IMC */
> -#define ICX_NUMBER_IMC_CHN			2
> +#define ICX_NUMBER_IMC_CHN			3
>   #define ICX_IMC_MEM_STRIDE			0x4
>   
>   /* SPR */
> @@ -5458,7 +5458,7 @@ static struct intel_uncore_ops icx_uncore_mmio_ops = {
>   static struct intel_uncore_type icx_uncore_imc = {
>   	.name		= "imc",
>   	.num_counters   = 4,
> -	.num_boxes	= 8,
> +	.num_boxes	= 12,
>   	.perf_ctr_bits	= 48,
>   	.fixed_ctr_bits	= 48,
>   	.fixed_ctr	= SNR_IMC_MMIO_PMON_FIXED_CTR,