Re: [PATCH v3 1/2] dt-bindings: dwmac: Add bindings for new Ingenic SoCs.

From: Rob Herring
Date: Tue Jun 15 2021 - 19:06:09 EST


On Mon, Jun 14, 2021 at 11:18 AM 周琰杰 (Zhou Yanjie)
<zhouyanjie@xxxxxxxxxxxxxx> wrote:
>
> Add the dwmac bindings for the JZ4775 SoC, the X1000 SoC,
> the X1600 SoC, the X1830 SoC and the X2000 SoC from Ingenic.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
> ---
>
> Notes:
> v1->v2:
> No change.
>
> v2->v3:
> Add "ingenic,mac.yaml" for Ingenic SoCs.
>
> .../devicetree/bindings/net/ingenic,mac.yaml | 76 ++++++++++++++++++++++
> .../devicetree/bindings/net/snps,dwmac.yaml | 15 +++++
> 2 files changed, 91 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/ingenic,mac.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/ingenic,mac.yaml b/Documentation/devicetree/bindings/net/ingenic,mac.yaml
> new file mode 100644
> index 00000000..5fe2e81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/ingenic,mac.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bindings for MAC in Ingenic SoCs
> +
> +maintainers:
> + - 周琰杰 (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
> +
> +description:
> + The Ethernet Media Access Controller in Ingenic SoCs.
> +
> +properties:
> + compatible:
> + enum:
> + - ingenic,jz4775-mac
> + - ingenic,x1000-mac
> + - ingenic,x1600-mac
> + - ingenic,x1830-mac
> + - ingenic,x2000-mac
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + const: macirq
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: stmmaceth
> +
> + mode-reg:
> + description: An extra syscon register that control ethernet interface and timing delay

Needs a vendor prefix and type.

> +
> + rx-clk-delay-ps:
> + description: RGMII receive clock delay defined in pico seconds
> +
> + tx-clk-delay-ps:
> + description: RGMII transmit clock delay defined in pico seconds
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - mode-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/x1000-cgu.h>
> +
> + mac: ethernet@134b0000 {
> + compatible = "ingenic,x1000-mac", "snps,dwmac";

Doesn't match the schema.

> + reg = <0x134b0000 0x2000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <55>;
> + interrupt-names = "macirq";
> +
> + clocks = <&cgu X1000_CLK_MAC>;
> + clock-names = "stmmaceth";
> +
> + mode-reg = <&mac_phy_ctrl>;
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> index 2edd8be..9c0ce92 100644
> --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> @@ -56,6 +56,11 @@ properties:
> - amlogic,meson8m2-dwmac
> - amlogic,meson-gxbb-dwmac
> - amlogic,meson-axg-dwmac
> + - ingenic,jz4775-mac
> + - ingenic,x1000-mac
> + - ingenic,x1600-mac
> + - ingenic,x1830-mac
> + - ingenic,x2000-mac
> - rockchip,px30-gmac
> - rockchip,rk3128-gmac
> - rockchip,rk3228-gmac
> @@ -310,6 +315,11 @@ allOf:
> - allwinner,sun8i-r40-emac
> - allwinner,sun8i-v3s-emac
> - allwinner,sun50i-a64-emac
> + - ingenic,jz4775-mac
> + - ingenic,x1000-mac
> + - ingenic,x1600-mac
> + - ingenic,x1830-mac
> + - ingenic,x2000-mac
> - snps,dwxgmac
> - snps,dwxgmac-2.10
> - st,spear600-gmac
> @@ -353,6 +363,11 @@ allOf:
> - allwinner,sun8i-r40-emac
> - allwinner,sun8i-v3s-emac
> - allwinner,sun50i-a64-emac
> + - ingenic,jz4775-mac
> + - ingenic,x1000-mac
> + - ingenic,x1600-mac
> + - ingenic,x1830-mac
> + - ingenic,x2000-mac
> - snps,dwmac-4.00
> - snps,dwmac-4.10a
> - snps,dwmac-4.20a
> --
> 2.7.4
>