Re: [PATCH] dt-bindings: serial: convert Cadence UART bindings to YAML

From: Rob Herring
Date: Mon Jun 14 2021 - 11:03:47 EST


On Mon, Jun 14, 2021 at 06:33:59AM +0900, Nobuhiro Iwamatsu wrote:
> Convert serial for Cadence UART bindings documentation to YAML.
>
> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/serial/cdns,uart.txt | 27 --------
> .../devicetree/bindings/serial/cdns,uart.yaml | 68 +++++++++++++++++++
> 2 files changed, 68 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.txt
> create mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.yaml
>
> diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt
> deleted file mode 100644
> index 4efc560f90abbd..00000000000000
> --- a/Documentation/devicetree/bindings/serial/cdns,uart.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -Binding for Cadence UART Controller
> -
> -Required properties:
> -- compatible :
> - Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
> - Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
> -- reg: Should contain UART controller registers location and length.
> -- interrupts: Should contain UART controller interrupts.
> -- clocks: Must contain phandles to the UART clocks
> - See ../clocks/clock-bindings.txt for details.
> -- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
> - See ../clocks/clock-bindings.txt for details.
> -
> -
> -Optional properties:
> -- cts-override : Override the CTS modem status signal. This signal will
> - always be reported as active instead of being obtained from the modem status
> - register. Define this if your serial port does not use this pin
> -
> -Example:
> - uart@e0000000 {
> - compatible = "cdns,uart-r1p8";
> - clocks = <&clkc 23>, <&clkc 40>;
> - clock-names = "uart_clk", "pclk";
> - reg = <0xE0000000 0x1000>;
> - interrupts = <0 27 4>;
> - };
> diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> new file mode 100644
> index 00000000000000..ce467fa464bfd0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence UART Controller Device Tree Bindings
> +
> +maintainers:
> + - Michal Simek <michal.simek@xxxxxxxxxx>
> +
> +allOf:
> + - $ref: /schemas/serial.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: UART controller for Zynq-7xxx SoC
> + items:
> + - enum:
> + - xlnx,xuartps
> + - cdns,uart-r1p8

What you want is:

items:
- const: xlnx,xuartps
- const: cdns,uart-r1p8

> + - description: UART controller for Zynq Ultrascale+ MPSoC
> + items:
> + - enum:
> + - xlnx,zynqmp-uart
> + - cdns,uart-r1p12
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: uart_clk
> + - const: pclk
> +
> + cts-override:
> + description: |
> + Override the CTS modem status signal. This signal will
> + always be reported as active instead of being obtained
> + from the modem status register. Define this if your serial
> + port does not use this pin.
> + type: boolean
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false

unevaluatedProperties: false

because you could have child nodes with attached devices.

> +
> +examples:
> + - |
> + serial@e0000000 {
> + compatible = "cdns,uart-r1p8";

This is wrong based on what the binding said.

> + clocks = <&clkc 23>, <&clkc 40>;
> + clock-names = "uart_clk", "pclk";
> + reg = <0xE0000000 0x1000>;
> + interrupts = <0 27 4>;
> + };
> --
> 2.32.0