Re: [RFC PATCH 3/5] arm64: aarch64-insn: Add barrier encodings

[Julien Thierry]

On 2/2/21 12:15 PM, Mark Rutland wrote:
> On Wed, Jan 20, 2021 at 06:17:43PM +0100, Julien Thierry wrote:
> > Create necessary functions to encode/decode aarch64 data/instruction
> > barriers.
> >
> > Signed-off-by: Julien Thierry <jthierry@xxxxxxxxxx>
> > ---
> >   arch/arm64/include/asm/aarch64-insn.h | 9 +++++++++
> >   1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm64/include/asm/aarch64-insn.h b/arch/arm64/include/asm/aarch64-insn.h
> > index 200bee726172..d0fee47bbe6e 100644
> > --- a/arch/arm64/include/asm/aarch64-insn.h
> > +++ b/arch/arm64/include/asm/aarch64-insn.h
> > @@ -379,6 +379,9 @@ __AARCH64_INSN_FUNCS(eret_auth,	0xFFFFFBFF, 0xD69F0BFF)
> >   __AARCH64_INSN_FUNCS(mrs,	0xFFF00000, 0xD5300000)
> >   __AARCH64_INSN_FUNCS(msr_imm,	0xFFF8F01F, 0xD500401F)
> >   __AARCH64_INSN_FUNCS(msr_reg,	0xFFF00000, 0xD5100000)
> > +__AARCH64_INSN_FUNCS(dmb,	0xFFFFF0FF, 0xD50330BF)
> > +__AARCH64_INSN_FUNCS(dsb,	0xFFFFF0FF, 0xD503309F)
> > +__AARCH64_INSN_FUNCS(isb,	0xFFFFF0FF, 0xD50330DF)
>
> These match the encodings in ARM DDI 0487G.a, with a couple of caveats
> for DSB.
>
> Per section C6.2.82 on page C6-1000, when CRm != 0x00, the instruction
> isn't considered a DSB. I believe per the "barriers" decode table on
> page C4-289 that here "0x00" is actually a binary string and 'x' is a
> "don't care" -- I've raised a ticket to get the documentation clarified.
> I suspect we need to write a function to handle that.

Ah, I did miss that part. Thanks for pointing it out (and for clarifying 
it's probably not hexa, but the binary string makes sense since it's a 4 
bits field)

> There's also a secondary encoding for DSB with FEAT_XS, which we don't
> currently use but might want to add.

Ah, yes, had to pick up a newer version of the Arm ARM! I'll add it.

> >   #undef	__AARCH64_INSN_FUNCS
> >   
> > @@ -390,6 +393,12 @@ static inline bool aarch64_insn_is_adr_adrp(u32 insn)
> >   	return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
> >   }
> >   
> > +static inline bool aarch64_insn_is_barrier(u32 insn)
> > +{
> > +	return aarch64_insn_is_dmb(insn) || aarch64_insn_is_dsb(insn) ||
> > +	       aarch64_insn_is_isb(insn);
> > +}
>
> I assume this is meant to match the barriers instruction class, as per
> the table on page C4-289? That also contains CLREX, SB, SSBB, and PSSBB,
> and it might be worth adding them at the same time.

Yes, I have to admit I only added the ones that objtool saw and 
complained about "unreachable instruction" (mostly barriers after 
ret/eret). I'll add them as well.

Thanks,

--
Julien Thierry