Re: [PATCH v1 1/7] coresight: etm-perf: Add support for PID tracing for kernel at EL2

[Suzuki K Poulose]

On 1/12/21 8:58 AM, Leo Yan wrote:
> Hi Mike,
>
> On Mon, Jan 11, 2021 at 04:22:39PM +0000, Mike Leach wrote:
>
> [...]
>
> > > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
> > > index b0e35eec6499..927c6285ce5d 100644
> > > --- a/include/linux/coresight-pmu.h
> > > +++ b/include/linux/coresight-pmu.h
> > > @@ -11,16 +11,19 @@
> > >   #define CORESIGHT_ETM_PMU_SEED  0x10
> > >
> > >   /* ETMv3.5/PTM's ETMCR config bit */
> > > -#define ETM_OPT_CYCACC  12
> > > -#define ETM_OPT_CTXTID 14
> > > -#define ETM_OPT_TS      28
> > > -#define ETM_OPT_RETSTK 29
> > > +#define ETM_OPT_CYCACC         12
> > > +#define ETM_OPT_CTXTID         14
> > > +#define ETM_OPT_CTXTID_IN_VMID 15
> >
> > Minor issue here - ETMv3.x / PTM cannot trace CXTID in VMID so this
> > may better be named ETM4_OPT_CTXTID_IN_VMID, rather than be grouped
> > with the ETM3.5 options?
>
> I looked into this suggestion but found it's complex than I assumed.
> This config bits are not only used for ETMv3.x / PTM, it's also used
> as an configuration interface between user space in Perf and kernel
> drivers.

Exactly. I believe this problematic. We are stuckwith using the ETM3.x/PTM
config bits for the CS_ETM pmu, which is a bit wierd and the allocation of
the config bits are sparse. The problem with changing them now, will break
older perf tools decoding a perf.data from a newer kernel. I believe we are
stuck with this.

I would recommend simply updating the comment to reflect that, thats the
generic CS PMU ABI for configuration which was initially based on ETM3.x.

Suzuki