Re: [PATCH v5 2/2] hwspinlock: add sun6i hardware spinlock support

[Wilken Gottwalt]

On Wed, 6 Jan 2021 11:15:42 +0100
Maxime Ripard <maxime@xxxxxxxxxx> wrote:

> On Wed, Dec 23, 2020 at 12:35:10PM +0100, Wilken Gottwalt wrote:
> > Adds the sun6i_hwspinlock driver for the hardware spinlock unit found in
> > most of the sun6i compatible SoCs.
> > 
> > This unit provides at least 32 spinlocks in hardware. The implementation
> > supports 32, 64, 128 or 256 32bit registers. A lock can be taken by
> > reading a register and released by writing a 0 to it. This driver
> > supports all 4 spinlock setups, but for now only the first setup (32
> > locks) seem to exist in available devices. This spinlock unit is shared
> > between all ARM cores and the embedded companion core. All of them can
> > take/release a lock with a single cycle operation. It can be used to
> > sync access to devices shared by the ARM cores and the companion core.
> > 
> > There are two ways to check if a lock is taken. The first way is to read
> > a lock. If a 0 is returned, the lock was free and is taken now. If an 1
> > is returned, the caller has to try again. Which means the lock is taken.
> > The second way is to read a 32bit wide status register where every bit
> > represents one of the 32 first locks. According to the datasheets this
> > status register supports only the 32 first locks. This is the reason the
> > first way (lock read/write) approach is used to be able to cover all 256
> > locks in future devices. The driver also reports the amount of supported
> > locks via debugfs.
> > 
> > Signed-off-by: Wilken Gottwalt <wilken.gottwalt@xxxxxxxxxx>
> 
> Reviewed-by: Maxime Ripard <mripard@xxxxxxxxxx>

Does it mean the driver is okay and I only need to fix the bindings
documentation? If so, would you prefer an updated patch set or only the
documentation patch in a new version?

> Thanks!
> Maxime