Re: [GIT pull] locking/urgent for v5.10-rc6

[Christian Borntraeger]

On 30.11.20 19:04, Linus Torvalds wrote:
> On Mon, Nov 30, 2020 at 5:03 AM Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
>>
>>> But but but...
>>>
>>>   do_idle()                   # IRQs on
>>>     local_irq_disable();      # IRQs off
>>>     defaul_idle_call()        # IRQs off
>>         lockdep_hardirqs_on();  # IRQs off, but lockdep things they're on
>>>       arch_cpu_idle()         # IRQs off
>>>         enabled_wait()        # IRQs off
>>>         raw_local_save()      # still off
>>>         psw_idle()            # very much off
>>>           ext_int_handler     # get an interrupt ?!?!
>>               rcu_irq_enter()   # lockdep thinks IRQs are on <- FAIL
>>
>> I can't much read s390 assembler, but ext_int_handler() has a
>> TRACE_IRQS_OFF, which would be sufficient to re-align the lockdep state
>> with the actual state, but there's some condition before it, what's that
>> test and is that right?
> 
> I think that "psw_idle()" enables interrupts, exactly like x86 does.

Yes, by definition.  Otherwise it would be an software error state.
The interesting part is the lpswe instruction at the end (load PSW) 
which loads the full PSW, which contains interrupt enablement, wait bit,
condition code, paging enablement, machine check enablement the address
and others. The idle psw is enabled for interrupts and has the wait bit
set. If the wait bit is set and interrupts are off this is called "disabled
wait" and is used for panic, shutdown etc. 

> See my previous email.
> 
> But no, I can't read s390 asm either. IBM is notorious for making up
> odd IBM-only incomprehensible names. When "oi" means "or immediate", I
> personally start suspecting that there were some "happy drugs"
> involved
> 
> To make matters worse, some of the assembly code in psw_idle isn't
> even assembly code, it's machine code, with "BPON" being an
> alternative instruction definition with just the hex encoding for the
> machine code instruction rather than any actual human-legible
> instruction encoding.
> 
> Of course, when the "human-legible" instructions are "oi", I guess hex
> codes aren't all that much less legible..
> 
> s390 programmers must be some super-human breed. Or, alternatively,
> they are munching happy pills by the truck-load to get over the pain
> ;)


For something that was defined in 1964 it is certainly not too bad.
And for the oddities, you simply get used to it.

In the end the scheme is actually relatively straightforward. 
The first character defines what it is:
o: or
a: add
n: and
l: load	
i: insert (kind of a load to parts, e.g. only one byte)
st: store
b: branch
j: jump
and some more but those should cover 80% of what you need.
and the following characters then tell if 32 or 64 bit (g), 
immediate (i) value or memory, type of register (float, general purpose).
so lg for a 64 bit load, l for a 32bit load. 
ld for a load into a floating point register (double)