Re: [PATCH v2 2/2] perf jevents: Add test for arch std events

[kajoljain]

On 10/22/20 4:32 PM, John Garry wrote:
> Recently there was an undetected breakage for std arch event support.
> 
> Add support in "PMU events" testcase to detect such breakages.
> 
> For this, the "test" arch needs has support added to process std arch
> events. And a test event is added for the test, ifself.
> 
> Also add a few code comments to help understand the code a bit better.

Patch looks good to me.

Reviewed-By: Kajol Jain<kjain@xxxxxxxxxxxxx>

Thanks,
Kajol Jain
> 
> Signed-off-by: John Garry <john.garry@xxxxxxxxxx>
> ---
>  .../perf/pmu-events/arch/test/arch-std-events.json |  8 ++++++++
>  .../perf/pmu-events/arch/test/test_cpu/cache.json  |  5 +++++
>  tools/perf/pmu-events/jevents.c                    |  4 ++++
>  tools/perf/tests/pmu-events.c                      | 14 ++++++++++++++
>  4 files changed, 31 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/test/arch-std-events.json
>  create mode 100644 tools/perf/pmu-events/arch/test/test_cpu/cache.json
> 
> diff --git a/tools/perf/pmu-events/arch/test/arch-std-events.json b/tools/perf/pmu-events/arch/test/arch-std-events.json
> new file mode 100644
> index 000000000000..43f6f729d6ae
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/test/arch-std-events.json
> @@ -0,0 +1,8 @@
> +[
> +    {
> +        "PublicDescription": "Attributable Level 3 cache access, read",
> +        "EventCode": "0x40",
> +        "EventName": "L3_CACHE_RD",
> +        "BriefDescription": "L3 cache access, read"
> +    }
> +]
> diff --git a/tools/perf/pmu-events/arch/test/test_cpu/cache.json b/tools/perf/pmu-events/arch/test/test_cpu/cache.json
> new file mode 100644
> index 000000000000..036d0efdb2bb
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/test/test_cpu/cache.json
> @@ -0,0 +1,5 @@
> +[
> +    {
> +	 "ArchStdEvent": "L3_CACHE_RD"
> +    }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
> index 7326c14c4623..72cfa3b5046d 100644
> --- a/tools/perf/pmu-events/jevents.c
> +++ b/tools/perf/pmu-events/jevents.c
> @@ -1162,6 +1162,10 @@ int main(int argc, char *argv[])
>  
>  	sprintf(ldirname, "%s/test", start_dirname);
>  
> +	rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0);
> +	if (rc)
> +		goto err_processing_std_arch_event_dir;
> +
>  	rc = nftw(ldirname, process_one_file, maxfds, 0);
>  	if (rc)
>  		goto err_processing_dir;
> diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c
> index d3517a74d95e..ad2b21591275 100644
> --- a/tools/perf/tests/pmu-events.c
> +++ b/tools/perf/tests/pmu-events.c
> @@ -14,8 +14,10 @@
>  #include "util/parse-events.h"
>  
>  struct perf_pmu_test_event {
> +	/* used for matching against events from generated pmu-events.c */
>  	struct pmu_event event;
>  
> +	/* used for matching against event aliases */
>  	/* extra events for aliases */
>  	const char *alias_str;
>  
> @@ -78,6 +80,17 @@ static struct perf_pmu_test_event test_cpu_events[] = {
>  		.alias_str = "umask=0,(null)=0x30d40,event=0x3a",
>  		.alias_long_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
>  	},
> +	{
> +		.event = {
> +			.name = "l3_cache_rd",
> +			.event = "event=0x40",
> +			.desc = "L3 cache access, read",
> +			.long_desc = "Attributable Level 3 cache access, read",
> +			.topic = "cache",
> +		},
> +		.alias_str = "event=0x40",
> +		.alias_long_desc = "Attributable Level 3 cache access, read",
> +	},
>  	{ /* sentinel */
>  		.event = {
>  			.name = NULL,
> @@ -357,6 +370,7 @@ static int __test__pmu_event_aliases(char *pmu_name, int *count)
>  }
>  
>  
> +/* Test that aliases generated are as expected */
>  static int test_aliases(void)
>  {
>  	struct perf_pmu *pmu = NULL;
>