[PATCH v2 5/6] dt-bindings: spi: Add compatible for Intel LGM SoC

[Ramuthevar,Vadivel MuruganX]

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx>

Add compatible string for Intel LGM SoC.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx>
---
 .../devicetree/bindings/spi/cadence-quadspi.yaml   | 68 +++++++++++-----------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
index 6ed8122a1326..57be1a730e7b 100644
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -14,65 +14,61 @@ allOf:
 
 properties:
   compatible:
-    items:
-      - const: cdns,qspi-nor
-      - const: ti,k2g-qspi, cdns,qspi-nor
-      - const: ti,am654-ospi, cdns,qspi-nor
-
-    description:
-      Should be one of the above supported compatible strings.
-      optional properties
-      "cdns,is-decoded-cs" - Flag to indicate whether decoder is used or not.
-      "cdns,rclk-en" - Flag to indicate that QSPI return clock is used to latch
-      the read data rather than the QSPI clock. Make sure that QSPI return
-      clock is populated on the board before using this property.
+    oneOf:
+      - items:
+         - const: cdns,qspi-nor
+         - const: ti,k2g-qspi, cdns,qspi-nor
+         - const: ti,am654-ospi, cdns,qspi-nor
 
   reg:
-    maxItems: 2
-    
-    description:
-      Contains two entries, each of which is a tuple consisting of a
-      physical address and length. The first entry is the address and
-      length of the controller register set. The second entry is the
-      address and length of the QSPI Controller data area.
+    items:
+      - description: the controller register set
+      - description: the controller data area
 
   interrupts:
     maxItems: 1
-    description:
-      Unit interrupt specifier for the controller interrupt.
 
   clocks:
     maxItems: 1
-    description:
-      phandle to the Quad SPI clock.
 
   cdns,fifo-depth:
     description:
       Size of the data FIFO in words.
-    allOf:
-      - $ref: "/schemas/types.yaml#/definitions/uint32"
-      - enum: [ 128, 256 ]
-      - default: 128
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    enum: [ 128, 256 ]
+    default: 128
 
   cdns,fifo-width:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
       Bus width of the data FIFO in bytes.
-    multipleOf: 4
+    default: 4
 
   cdns,trigger-address:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
       32-bit indirect AHB trigger address.
 
+  cdns,is-decoded-cs:
+    type: boolean
+    description:
+      Flag to indicate whether decoder is used or not.
+
+  cdns,rclk-en:
+    type: boolean
+    description:
+      Flag to indicate that QSPI return clock is used to latch the read
+      data rather than the QSPI clock. Make sure that QSPI return clock
+      is populated on the board before using this property.
+
   resets:
-     description:
-       Must contain an entry for each entry in reset-names.
-       See ../reset/reset.txt for details.
+    maxItems : 2
 
   reset-names:
-    description:
-      Must include either "qspi" and/or "qspi-ocp".
+    minItems: 1
+    maxItems: 2
+    items:
+      enum: [ qspi, qspi-ocp ]
 
 # subnode's properties
 patternProperties:
@@ -114,13 +110,17 @@ required:
   - cdns,fifo-depth
   - cdns,fifo-width
   - cdns,trigger-address
+  - cdns,is-decoded-cs
+  - cdns,rclk-en
   - resets
   - reset-names
 
+additionalProperties: false
+
 examples:
   - |
     qspi: spi@ff705000 {
-      compatible = "cadence,qspi";
+      compatible = "cadence,qspi","cdns,qpsi-nor";
       #address-cells = <1>;
       #size-cells = <0>;
       reg = <0xff705000 0x1000>,
-- 
2.11.0