[PATCH RFC] bus: mhi: core: Enable unique QRTR node ID support

[Gokul Sriram Palanisamy]

On multi-mhi platforms, host WiFi driver and
QMI test driver needs to differntiate between
QMI packets received from multiple mhi devices.

With QCN9000 PCI cards, once SBL gets loaded, we
utilize ERRDBG2 register to write a unique value
per mhi device from device-tree that the device
utilizes to set a unique QRTR node ID and
instance ID for the QMI service. This helps QRTR
stack in differenting the packets in a multi-mhi
environment and can route them accordingly.

sample:
root@OpenWrt:/# qrtr-lookup
  Service Version Instance Node  Port
       69       1       40   40     2 ATH10k WLAN firmware service
       15       1        0   40     1 Test service
       69       1       39   39     2 ATH10k WLAN firmware service
       15       1        0   39     1 Test service

Here on column 4, 39 and 40 are the node IDs that
is unique per mhi device.

Signed-off-by: Gokul Sriram Palanisamy <gokulsri@xxxxxxxxxxxxxx>
---
 .../devicetree/bindings/mhi/qcom,mhi.yaml          | 36 ++++++++++++++++++++++
 drivers/bus/mhi/core/boot.c                        | 14 +++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mhi/qcom,mhi.yaml

diff --git a/Documentation/devicetree/bindings/mhi/qcom,mhi.yaml b/Documentation/devicetree/bindings/mhi/qcom,mhi.yaml
new file mode 100644
index 0000000..f763e9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mhi/qcom,mhi.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/pci/qcom,pcie.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Qualcomm Modem Host Interface
+
+maintainers:
+  - Gokul Sriram Palanisamy <gokulsri@xxxxxxxxxxxxxx>
+
+properties:
+  qrtr-instance-id:
+    const: 32
+
+required:
+  - reg
+  - qrtr-instance-id
+
+examples:
+  - |
+    pcie: pci@10000000 {
+        compatible = "qcom,pcie-qcs404";
+        status = "ok";
+        perst-gpio = <&tlmm 58 0x1>;
+
+        pcie0_rp: pcie0_rp {
+            reg = <0 0 0 0 0>;
+            status = "ok";
+            mhi_0: qcom,mhi@0 {
+                reg = <0 0 0 0 0 >;
+                qrtr_instance_id = <0x20>;
+            };
+        };
+    };
diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c
index 0b38014..7406f28 100644
--- a/drivers/bus/mhi/core/boot.c
+++ b/drivers/bus/mhi/core/boot.c
@@ -18,6 +18,9 @@
 #include <linux/wait.h>
 #include "internal.h"
 
+#define QRTR_INSTANCE_MASK	0x0000FFFF
+#define QRTR_INSTANCE_SHIFT	0
+
 /* Setup RDDM vector table for RDDM transfer and program RXVEC */
 void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,
 		      struct image_info *img_info)
@@ -445,6 +448,17 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
 		return;
 	}
 
+	if (!ret && mhi_cntrl->cntrl_dev->of_node) {
+		ret = of_property_read_u32(mhi_cntrl->cntrl_dev->of_node,
+					   "qrtr-instance-id", &instance);
+		if (!ret) {
+			instance &= QRTR_INSTANCE_MASK;
+			mhi_write_reg_field(mhi_cntrl, mhi_cntrl->bhi,
+					    BHI_ERRDBG2, QRTR_INSTANCE_MASK,
+					    QRTR_INSTANCE_SHIFT, instance);
+		}
+	}
+
 	if (mhi_cntrl->ee == MHI_EE_EDL)
 		return;
 
-- 
2.7.4