Re: [PATCH v3 02/18] iommu/vt-d: Add DEV-MSI support

[David Woodhouse]

On Wed, 2020-09-30 at 20:32 +0200, Thomas Gleixner wrote:
> On Tue, Sep 15 2020 at 16:27, Dave Jiang wrote:
> > @@ -1303,9 +1303,10 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
> >  	case X86_IRQ_ALLOC_TYPE_HPET:
> >  	case X86_IRQ_ALLOC_TYPE_PCI_MSI:
> >  	case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
> > +	case X86_IRQ_ALLOC_TYPE_DEV_MSI:
> >  		if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
> >  			set_hpet_sid(irte, info->devid);
> > -		else
> > +		else if (info->type != X86_IRQ_ALLOC_TYPE_DEV_MSI)
> >  			set_msi_sid(irte,
> >  			msi_desc_to_pci_dev(info->desc));
> 
> Gah. this starts to become unreadable.
> 
> diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c
> index 8f4ce72570ce..0c1ea8ceec31 100644
> --- a/drivers/iommu/intel/irq_remapping.c
> +++ b/drivers/iommu/intel/irq_remapping.c
> @@ -1271,6 +1271,16 @@ static struct irq_chip intel_ir_chip = {
>  	.irq_set_vcpu_affinity	= intel_ir_set_vcpu_affinity,
>  };
>  
> +static void irte_prepare_msg(struct msi_msg *msg, int index, int subhandle)
> +{
> +	msg->address_hi = MSI_ADDR_BASE_HI;
> +	msg->data = sub_handle;
> +	msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
> +			  MSI_ADDR_IR_SHV |
> +			  MSI_ADDR_IR_INDEX1(index) |
> +			  MSI_ADDR_IR_INDEX2(index);
> +}
> +
>  static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
>  					     struct irq_cfg *irq_cfg,
>  					     struct irq_alloc_info *info,
> @@ -1312,19 +1322,18 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
>  		break;
>  
>  	case X86_IRQ_ALLOC_TYPE_HPET:
> +		set_hpet_sid(irte, info->hpet_id);
> +		irte_prepare_msg(msg, index, sub_handle);
> +		break;
> +
>  	case X86_IRQ_ALLOC_TYPE_MSI:
>  	case X86_IRQ_ALLOC_TYPE_MSIX:
> -		if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
> -			set_hpet_sid(irte, info->hpet_id);
> -		else
> -			set_msi_sid(irte, info->msi_dev);
> -
> -		msg->address_hi = MSI_ADDR_BASE_HI;
> -		msg->data = sub_handle;
> -		msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
> -				  MSI_ADDR_IR_SHV |
> -				  MSI_ADDR_IR_INDEX1(index) |
> -				  MSI_ADDR_IR_INDEX2(index);
> +		set_msi_sid(irte, info->msi_dev);
> +		irte_prepare_msg(msg, index, sub_handle);
> +		break;
> +
> +	case X86_IRQ_ALLOC_TYPE_DEV_MSI:
> +		irte_prepare_msg(msg, index, sub_handle);
>  		break;
>  
>  	default:
> 
> Hmm?

It'd get a bit nicer if you *always* did the irte_prepare_msg() part to
generate the MSI message. Let the IOAPIC driver swizzle that into the
IOAPIC RTE for itself. You have no business composing an IOAPIC RTE
here.

Then your switch statement is *only* for setting the SID in the IRTE
appropriately.

Attachment: smime.p7s
Description: S/MIME cryptographic signature