RE: [RFC,net-next,v1, 1/1] net: stmmac: Enable SERDES power up/down sequence

[Voon, Weifeng]

> > This patch is to enable Intel SERDES power up/down sequence. The
> > SERDES converts 8/10 bits data to SGMII signal. Below is an example of
> > HW configuration for SGMII mode. The SERDES is located in the PHY IF
> > in the diagram below.
> >
> > <-----------------GBE Controller---------->|<--External PHY chip-->
> > +----------+         +----+            +---+           +----------+
> > |   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External |
> > |   MAC    |         |xPCS|            |IF |           | PHY      |
> > +----------+         +----+            +---+           +----------+
> >        ^               ^                 ^                ^
> >        |               |                 |                |
> >        +---------------------MDIO-------------------------+
> >
> > PHY IF configuration and status registers are accessible through mdio
> > address 0x15 which is defined as intel_adhoc_addr. During D0, The
> > driver will need to power up PHY IF by changing the power state to P0.
> > Likewise, for D3, the driver sets PHY IF power state to P3.
> 
> I don't think this is the right approach.
> 
> You could just add a new "mdio-intel-serdes" to phy/ folder just like I
> did with XPCS because this is mostly related with PHY settings rather
> than EQoS.
I am taking this approach to put it in stmmac folder rather than phy folder
as a generic mdio-intel-serdes as this is a specific Intel serdes architecture which
would only pair with DW EQos and DW xPCS HW. Since this serdes will not able to
pair other MAC or other non-Intel platform, I would like you to reconsider this
approach. I am open for discussion. 
Thanks Jose for the fast response.

Regards,
Weifeng  

> 
> Perhaps Andrew has better insight on this.
> 
> BTW, are you using the standard XPCS helpers in phy/ folder ? Is it
> working fine for you ?
> 
> ---
> Thanks,
> Jose Miguel Abreu