Re: [PATCH v2 2/2] PCI: uniphier: Add UniPhier PCIe endpoint controller support

[Kunihiko Hayashi]

Hi Bjorn,

Thank you for your comment.

On Thu, 19 Mar 2020 12:06:59 -0500 <helgaas@xxxxxxxxxx> wrote:

> On Thu, Mar 19, 2020 at 04:54:09PM +0900, Kunihiko Hayashi wrote:
> > This introduces specific glue layer for UniPhier platform to support
> > PCIe controller that is based on the DesignWare PCIe core, and
> > this driver supports endpoint mode. This supports for Pro5 SoC only.
> 
> Possible alternate text: ("specific glue layer" isn't the usual way to
> describe a driver)
> 
>   PCI: uniphier: Add Socionext UniPhier Pro5 SoC endpoint controller driver
> 
>   Add driver for the Socionext UniPhier Pro5 SoC endpoint controller.
>   This controller is based on the DesignWare PCIe core.

I see. I'll accept your suggestion for the commit log.

> > +/* assertion time of intx in usec */
> 
> s/intx/INTx/ to match usage in spec (and in comments below :))

Certainly this isn't unified. I'll fix it.

> > +#define PCL_INTX_WIDTH_USEC		30
> 
> > +struct uniphier_pcie_ep_soc_data {
> > +	bool is_legacy;
> 
> I'd prefer "unsigned int is_legacy:1".  See [1].
> 
> But AFAICT you actually don't need this at all (yet), since you only
> have a single of_device_id, and it sets "is_legacy = true".  That
> means the *not* legacy code is effectively dead and hasn't been
> tested.

Yes.
Now I know the difference about between legacy and non-legacy SoC,
however, currently the driver doesn't have any non-legacy SoC support.

> My preference would be to add "is_legacy" and the associated tests
> when you actually *need* them, i.e., when you add support for a
> non-legacy device.

Agreed. The test for non-legacy SoC is necessary.
So I'll remove 'is_legacy' and related coded, and rewrite this driver
to support only legacy device.

And I'll remember [1] when adding non-legacy support.

> > +static int uniphier_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep)
> > +{
> > +	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > +	struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
> > +	u32 val;
> > +
> > +	/* assert INTx */
> > +	val = readl(priv->base + PCL_APP_INTX);
> > +	val |= PCL_APP_INTX_SYS_INT;
> > +	writel(val, priv->base + PCL_APP_INTX);
> > +
> > +	udelay(PCL_INTX_WIDTH_USEC);
> > +
> > +	/* deassert INTx */
> > +	val = readl(priv->base + PCL_APP_INTX);
> 
> Why do you need to read PCL_APP_INTX again here?

Indeed. This 'readl' isn't unnecessary.

> > +	val &= ~PCL_APP_INTX_SYS_INT;
> > +	writel(val, priv->base + PCL_APP_INTX);
> > +
> > +	return 0;
> > +}
> 
> > +	ret = dw_pcie_ep_init(ep);
> > +	if (ret) {
> > +		dev_err(dev, "Failed to initialize endpoint (%d)\n", ret);
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> 
> This is equivalent to:
> 
>   ret = dw_pcie_ep_init(ep);
>   if (ret)
>     dev_err(dev, "Failed to initialize endpoint (%d)\n", ret);
> 
>   return ret;

Agreed. I'll rewrite it next.

> 
> > +}
> 
> [1] https://lore.kernel.org/linux-fsdevel/CA+55aFzKQ6Pj18TB8p4Yr0M4t+S+BsiHH=BJNmn=76-NcjTj-g@xxxxxxxxxxxxxx/

Thank you,

---
Best Regards,
Kunihiko Hayashi