Re: [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations

[Wesley Cheng]

Hi Stephen,

Thanks for the feedback.

On 3/16/2020 10:03 AM, Stephen Boyd wrote:
> Quoting Wesley Cheng (2020-03-14 00:51:58)
>> Add the USB3 PIPE clock structures, so that the USB driver can
>> vote for the GCC to enable/disable it when required.  This clock
>> is needed for SSUSB operation.
>>
>> Signed-off-by: Wesley Cheng <wcheng@xxxxxxxxxxxxxx>
>> ---
>>  drivers/clk/qcom/gcc-sm8150.c | 26 ++++++++++++++++++++++++++
> 
> Can you please combine these two patches and add sm8150 in the subject?
> 

Sure, I'll combine the two patches into one and include the SM8150 tag
in the subject on the next patch series.

>>  1 file changed, 26 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
>> index d0cd03d..ef98fdc 100644
>> --- a/drivers/clk/qcom/gcc-sm8150.c
>> +++ b/drivers/clk/qcom/gcc-sm8150.c
>> @@ -3172,6 +3172,18 @@ enum {
>>         },
>>  };
>>  
>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>> +       .halt_check = BRANCH_HALT_SKIP,
>> +       .clkr = {
>> +               .enable_reg = 0xf058,
>> +               .enable_mask = BIT(0),
>> +               .hw.init = &(struct clk_init_data){
>> +                       .name = "gcc_usb3_prim_phy_pipe_clk",
>> +                       .ops = &clk_branch2_ops,
>> +               },
>> +       },
>> +};
>> +
>>  static struct clk_branch gcc_usb3_sec_clkref_clk = {
>>         .halt_reg = 0x8c028,
>>         .halt_check = BRANCH_HALT,
>> @@ -3219,6 +3231,18 @@ enum {
>>         },
>>  };
>>  
>> +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
>> +       .halt_check = BRANCH_HALT_SKIP,
> 
> Sad to see that we'll never resolve this.
> 

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