[PATCH v2 0/4] Fix some 4-byte vs. 8-byte alignment issues in atomic bit operations

[Fenghua Yu]

A split lock is an unaligned atomic operation that spans two cache
lines. The split lock access needs to hold bus lock and will
degrade performance.

Accessing one split lock long can take over one thousand extra cycles
than atomically accessing one unaligned long within one cache line.
And while the split lock access holds the bus lock, any other
memory accesses are not allowed and the overall memory access performance
is degraded.

Because badly performance impact by split lock, this patch series
solve the split lock issues instead of other alignment issues.

These parts are all simple fixes which are a necessary pre-cursor 
before we can enable #AC traps for split lock access. But they 
are also worthwhile performance fixes in their own right. So 
no sense in holding them back while we discuss the merits of 
the rest of the series. 

The alignment issues may be fixed by changing the atomic bit operations
APIs e.g. new set_bit_32() for 4-byte alignment. But the fixes will
be complex because they touch a lot of call sites and architectures.

Change Log:
v2:
- Remove patch 1 and 3 in v1 because they are in the tip tree already.
- Add new patches 2-4 per David Laight's comments:
https://lore.kernel.org/lkml/e7c75de9191847ed98c573f9ad871518@xxxxxxxxxxxxxxxx/
Running "grep -r --include '*.[ch]' '_bit([^(]*, *([^)]*\*)' ."
returns about 200 results. Most of them don't have split lock issues.

Fenghua Yu (3):
  xen-pcifront: Align address of flags to size of unsigned long
  mtd: rawnand: fsmc: Change to non-atomic bit operations
  x86/mce: Force alignment for atomic bit operations

Peter Zijlstra (1):
  drivers/net/b44: Change to non-atomic bit operations

 arch/x86/include/asm/mce.h          | 3 ++-
 drivers/mtd/nand/raw/fsmc_nand.c    | 4 ++--
 drivers/net/ethernet/broadcom/b44.c | 4 ++--
 include/xen/interface/io/pciif.h    | 7 +++++--
 4 files changed, 11 insertions(+), 7 deletions(-)

-- 
2.19.1