Re: [PATCH v10 6/6] x86/split_lock: Enable split lock detection by kernel parameter

[Peter Zijlstra]

On Thu, Nov 21, 2019 at 01:01:08PM -0800, Andy Lutomirski wrote:
> 
> > On Nov 21, 2019, at 11:56 AM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > 
> > ïOn Thu, Nov 21, 2019 at 09:51:03AM -0800, Andy Lutomirski wrote:
> > 
> >> Can we really not just change the lock asm to use 32-bit accesses for
> >> set_bit(), etc?  Sure, it will fail if the bit index is greater than
> >> 2^32, but that seems nuts.
> > 
> > There are 64bit architectures that do exactly that: Alpha, IA64.
> > 
> > And because of the byte 'optimization' from x86 we already could not
> > rely on word atomicity (we actually play games with multi-bit atomicity
> > for PG_waiters and clear_bit_unlock_is_negative_byte).
> 
> I read a couple pages of the paper you linked and I didnât spot what
> youâre talking about as it refers to x86.  What are the relevant word
> properties of x86 bitops or the byte optimization?

The paper mostly deals with Power and ARM, x86 only gets sporadic
mention. It does present a way to reason about mixed size atomic
operations though.

And the bitops API is very much cross-architecture. And like I wrote in
that other email, having audited the atomic bitop width a number of
times now makes me say no to anything complicated.