[PATCH] cpufreq: sun50i: Fix CPU speed bin detection

[Ondrej Jirman]

I have failures to boot on Orange Pi 3, because this driver determined
that my SoC is from the normal bin, but my SoC only works reliably with
the OPP values for the slowest bin.

Looking at BSP code, I found that efuse values have following meanings
on H6:

- 0b000 invalid (interpreted in vendor's BSP as normal bin)
- 0b001 slowest bin
- 0b011 normal bin
- 0b111 fastest bin

Let's play it safe and interpret 0 as the slowest bin, but fix detection
of other bins to match vendor code.

Fixes: f328584f7bff ("cpufreq: Add sun50i nvmem based CPU scaling driver")
Signed-off-by: Ondrej Jirman <megous@xxxxxxxxxx>
---

See https://megous.com/git/linux/tree/drivers/soc/sunxi/sunxi-sid.c?h=h6-4.9-bsp#n484
and https://megous.com/git/linux/tree/drivers/cpufreq/sunxi-cpufreq.c?h=h6-4.9-bsp#n428
(1 is substracted from soc_bin number here!)

 drivers/cpufreq/sun50i-cpufreq-nvmem.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index df35ef3ef567..41dad03e245c 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -71,9 +71,12 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
 	efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
 	switch (efuse_value) {
 	case 0b0001:
-		*versions = 1;
+		*versions = 0;
 		break;
 	case 0b0011:
+		*versions = 1;
+		break;
+	case 0b0111:
 		*versions = 2;
 		break;
 	default:
-- 
2.23.0