Re: [alsa-devel] [RFC PATCH 26/40] soundwire: cadence_master: fix divider setting in clock register

From: Pierre-Louis Bossart
Date: Mon Aug 05 2019 - 11:41:24 EST



@@ -988,9 +989,11 @@ int sdw_cdns_init(struct sdw_cdns *cdns)
/* Set clock divider */
divider = (prop->mclk_freq / prop->max_clk_freq) - 1;
val = cdns_readl(cdns, CDNS_MCP_CLK_CTRL0);

reg read of CLK_CTRL0 can be removed.

yes for both comments. Thanks for the review Sanyog, appreciate it.


- val |= divider;
- cdns_writel(cdns, CDNS_MCP_CLK_CTRL0, val);
- cdns_writel(cdns, CDNS_MCP_CLK_CTRL1, val);
+
+ cdns_updatel(cdns, CDNS_MCP_CLK_CTRL0,
+ CDNS_MCP_CLK_MCLKD_MASK, divider);
+ cdns_updatel(cdns, CDNS_MCP_CLK_CTRL1,
+ CDNS_MCP_CLK_MCLKD_MASK, divider);
pr_err("plb: mclk %d max_freq %d divider %d register %x\n",
prop->mclk_freq,
@@ -1064,8 +1067,7 @@ int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params)
mcp_clkctrl_off = CDNS_MCP_CLK_CTRL0;
mcp_clkctrl = cdns_readl(cdns, mcp_clkctrl_off);

same as above.

- mcp_clkctrl |= divider;
- cdns_writel(cdns, mcp_clkctrl_off, mcp_clkctrl);
+ cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
pr_err("plb: mclk * 2 %d curr_dr_freq %d divider %d register %x\n",
prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR,
--
2.20.1