Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

[Aneesh Kumar K.V]

On 7/9/19 7:50 AM, Oliver O'Halloran wrote:
> On Tue, Jul 9, 2019 at 12:22 AM Aneesh Kumar K.V
> <aneesh.kumar@xxxxxxxxxxxxx> wrote:
> > Christophe Leroy <christophe.leroy@xxxxxx> writes:
> >
> > > *snip*
> > > +     if (IS_ENABLED(CONFIG_PPC64))
> > > +             isync();
> > >   }
> >
> >
> > Was checking with Michael about why we need that extra isync. Michael
> > pointed this came via
> >
> > https://github.com/mpe/linux-fullhistory/commit/faa5ee3743ff9b6df9f9a03600e34fdae596cfb2#diff-67c7ffa8e420c7d4206cae4a9e888e14
> >
> > for 970 which doesn't have coherent icache. So possibly isync there is
> > to flush the prefetch instructions? But even so we would need an icbi
> > there before that isync.
>
> I don't think it's that, there's some magic in flush_icache_range() to
> handle dropping prefetched instructions on 970.
>
> > So overall wondering why we need that extra barriers there.
>
> I think the isync is needed there because the architecture only
> requires sync to provide ordering. A sync alone doesn't guarantee the
> dcbfs have actually completed so the isync is necessary to ensure the
> flushed cache lines are back in memory. That said, as far as I know
> all the IBM book3s chips from power4 onwards will wait for pending
> dcbfs when they hit a sync, but that might change in the future.

ISA doesn't list that as the sequence. Only place where isync was 
mentioned was w.r.t  icbi where want to discards the prefetch.



> If it's a problem we could add a cpu-feature section around the isync
> to no-op it in the common case. However, when I had a look with perf
> it always showed that the sync was the hotspot so I don't think it'll
> help much.

What about the preceding barriers (sync; isync;) before dcbf? Why are 
they needed?

-aneesh