Re: [PATCH 1/1] i2c: iproc: Add multi byte read-write support for slave mode
From: Ray Jui
Date: Thu May 09 2019 - 13:12:02 EST
On 5/9/2019 10:03 AM, Rayagonda Kokatanur wrote:
> No change, it's just duplicate, please ignore.Â
>
> I am not able to find my patch over network , I tried sending second
> time by setting plain text mode, but still it's not visible.
>
I can see your patch from the linux-i2c mailing list:
https://patchwork.ozlabs.org/project/linux-i2c/list/
> Best regardsÂ
> Rayagonda
>
> On Thu, May 9, 2019, 9:58 PM Ray Jui <ray.jui@xxxxxxxxxxxx
> <mailto:ray.jui@xxxxxxxxxxxx> wrote:
>
> Why is the email sent twice? What has changed?
>
> On 5/8/2019 9:21 PM, Rayagonda Kokatanur wrote:
> > Add multiple byte read-write support for slave mode.
> >
> > Signed-off-by: Rayagonda Kokatanur
> <rayagonda.kokatanur@xxxxxxxxxxxx
> <mailto:rayagonda.kokatanur@xxxxxxxxxxxx>>
> > Signed-off-by: Srinath Mannam <srinath.mannam@xxxxxxxxxxxx
> <mailto:srinath.mannam@xxxxxxxxxxxx>>
> > ---
> >Â drivers/i2c/busses/i2c-bcm-iproc.c | 117
> +++++++++++++++++--------------------
> >Â 1 file changed, 53 insertions(+), 64 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c
> b/drivers/i2c/busses/i2c-bcm-iproc.c
> > index a845b8d..2c7f145 100644
> > --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> > +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
> > @@ -165,12 +165,6 @@ enum i2c_slave_read_status {
> >Â Â Â ÂI2C_SLAVE_RX_END,
> >Â };
> >Â
> > -enum i2c_slave_xfer_dir {
> > -Â Â ÂI2C_SLAVE_DIR_READ = 0,
> > -Â Â ÂI2C_SLAVE_DIR_WRITE,
> > -Â Â ÂI2C_SLAVE_DIR_NONE,
> > -};
> > -
> >Â enum bus_speed_index {
> >Â Â Â ÂI2C_SPD_100K = 0,
> >Â Â Â ÂI2C_SPD_400K,
> > @@ -203,7 +197,6 @@ struct bcm_iproc_i2c_dev {
> >Â Â Â Âstruct i2c_msg *msg;
> >Â
> >Â Â Â Âstruct i2c_client *slave;
> > -Â Â Âenum i2c_slave_xfer_dir xfer_dir;
> >Â
> >Â Â Â Â/* bytes that have been transferred */
> >Â Â Â Âunsigned int tx_bytes;
> > @@ -219,7 +212,8 @@ struct bcm_iproc_i2c_dev {
> >Â Â Â Â Â Â Â Â| BIT(IS_M_RX_THLD_SHIFT))
> >Â
> >Â #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
> > -Â Â Â Â Â Â Â| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT))
> > +Â Â Â Â Â Â Â| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
> > +Â Â Â Â Â Â Â| BIT(IS_S_TX_UNDERRUN_SHIFT))
> >Â
> >Â static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
> >Â static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
> > @@ -297,15 +291,11 @@ static void bcm_iproc_i2c_slave_init(
> >Â Â Â Â/* clear all pending slave interrupts */
> >Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
> >Â
> > -Â Â Â/* Enable interrupt register for any READ event */
> > -Â Â Âval = BIT(IE_S_RD_EVENT_SHIFT);
> >Â Â Â Â/* Enable interrupt register to indicate a valid byte in
> receive fifo */
> > -Â Â Âval |= BIT(IE_S_RX_EVENT_SHIFT);
> > +Â Â Âval = BIT(IE_S_RX_EVENT_SHIFT);
> >Â Â Â Â/* Enable interrupt register for the Slave BUSY command */
> >Â Â Â Âval |= BIT(IE_S_START_BUSY_SHIFT);
> >Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> > -
> > -Â Â Âiproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
> >Â }
> >Â
> >Â static void bcm_iproc_i2c_check_slave_status(
> > @@ -314,8 +304,11 @@ static void bcm_iproc_i2c_check_slave_status(
> >Â Â Â Âu32 val;
> >Â
> >Â Â Â Âval = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
> > -Â Â Âval = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
> > +Â Â Â/* status is valid only when START_BUSY is cleared after it
> was set */
> > +Â Â Âif (val & BIT(S_CMD_START_BUSY_SHIFT))
> > +Â Â Â Â Â Â Âreturn;
> >Â
> > +Â Â Âval = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
> >Â Â Â Âif (val == S_CMD_STATUS_TIMEOUT) {
> >Â Â Â Â Â Â Â Âdev_err(iproc_i2c->device, "slave random stretch
> time timeout\n");
> >Â
> > @@ -327,70 +320,66 @@ static void bcm_iproc_i2c_check_slave_status(
> >Â }
> >Â
> >Â static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev
> *iproc_i2c,
> > -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âu32 status)
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âu32 status)
> >Â {
> > -Â Â Âu8 value;
> >Â Â Â Âu32 val;
> > -Â Â Âu32 rd_status;
> > -Â Â Âu32 tmp;
> > +Â Â Âu8 value, rx_status;
> >Â
> > -Â Â Â/* Start of transaction. check address and populate the
> direction */
> > -Â Â Âif (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) {
> > -Â Â Â Â Â Â Âtmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
> > -Â Â Â Â Â Â Ârd_status = (tmp >> S_RX_STATUS_SHIFT) &
> S_RX_STATUS_MASK;
> > -Â Â Â Â Â Â Â/* This condition checks whether the request is a
> new request */
> > -Â Â Â Â Â Â Âif (((rd_status == I2C_SLAVE_RX_START) &&
> > -Â Â Â Â Â Â Â Â Â Â Â(status & BIT(IS_S_RX_EVENT_SHIFT))) ||
> > -Â Â Â Â Â Â Â Â Â Â Â((rd_status == I2C_SLAVE_RX_END) &&
> > -Â Â Â Â Â Â Â Â Â Â Â(status & BIT(IS_S_RD_EVENT_SHIFT)))) {
> > -
> > -Â Â Â Â Â Â Â Â Â Â Â/* Last bit is W/R bit.
> > -Â Â Â Â Â Â Â Â Â Â Â * If 1 then its a read request(by master).
> > -Â Â Â Â Â Â Â Â Â Â Â */
> > -Â Â Â Â Â Â Â Â Â Â Âiproc_i2c->xfer_dir = tmp &
> SLAVE_READ_WRITE_BIT_MASK;
> > -Â Â Â Â Â Â Â Â Â Â Âif (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)
> > -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_READ_REQUESTED,
> &value);
> > -Â Â Â Â Â Â Â Â Â Â Âelse
> > -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > +Â Â Â/* Slave RX byte receive */
> > +Â Â Âif (status & BIT(IS_S_RX_EVENT_SHIFT)) {
> > +Â Â Â Â Â Â Âval = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
> > +Â Â Â Â Â Â Ârx_status = (val >> S_RX_STATUS_SHIFT) &
> S_RX_STATUS_MASK;
> > +Â Â Â Â Â Â Âif (rx_status == I2C_SLAVE_RX_START) {
> > +Â Â Â Â Â Â Â Â Â Â Â/* Start of SMBUS for Master write */
> > +Â Â Â Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> >Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_WRITE_REQUESTED,
> &value);
> > -Â Â Â Â Â Â Â}
> > -Â Â Â}
> >Â
> > -Â Â Â/* read request from master */
> > -Â Â Âif ((status & BIT(IS_S_RD_EVENT_SHIFT)) &&
> > -Â Â Â Â Â Â Â(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) {
> > -Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > -Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_READ_PROCESSED, &value);
> > -Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> > +Â Â Â Â Â Â Â Â Â Â Âval = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
> > +Â Â Â Â Â Â Â Â Â Â Âvalue = (u8)((val >> S_RX_DATA_SHIFT) &
> S_RX_DATA_MASK);
> > +Â Â Â Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_WRITE_RECEIVED,
> &value);
> > +Â Â Â Â Â Â Â} else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > +Â Â Â Â Â Â Â Â Â Â Â/* Start of SMBUS for Master Read */
> > +Â Â Â Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_READ_REQUESTED,
> &value);
> > +Â Â Â Â Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> >Â
> > -Â Â Â Â Â Â Âval = BIT(S_CMD_START_BUSY_SHIFT);
> > -Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> > -Â Â Â}
> > +Â Â Â Â Â Â Â Â Â Â Âval = BIT(S_CMD_START_BUSY_SHIFT);
> > +Â Â Â Â Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> >Â
> > -Â Â Â/* write request from master */
> > -Â Â Âif ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
> > -Â Â Â Â Â Â Â(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) {
> > -Â Â Â Â Â Â Âval = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
> > -Â Â Â Â Â Â Â/* Its a write request by Master to Slave.
> > -Â Â Â Â Â Â Â * We read data present in receive FIFO
> > -Â Â Â Â Â Â Â */
> > -Â Â Â Â Â Â Âvalue = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
> > +Â Â Â Â Â Â Â Â Â Â Â/*
> > +Â Â Â Â Â Â Â Â Â Â Â * Enable interrupt for TX FIFO becomes
> empty and
> > +Â Â Â Â Â Â Â Â Â Â Â * less than PKT_LENGTH bytes were output on
> the SMBUS
> > +Â Â Â Â Â Â Â Â Â Â Â */
> > +Â Â Â Â Â Â Â Â Â Â Âval = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> > +Â Â Â Â Â Â Â Â Â Â Âval |= BIT(IE_S_TX_UNDERRUN_SHIFT);
> > +Â Â Â Â Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> > +Â Â Â Â Â Â Â} else {
> > +Â Â Â Â Â Â Â Â Â Â Â/* Master write other than start */
> > +Â Â Â Â Â Â Â Â Â Â Âvalue = (u8)((val >> S_RX_DATA_SHIFT) &
> S_RX_DATA_MASK);
> > +Â Â Â Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_WRITE_RECEIVED,
> &value);
> > +Â Â Â Â Â Â Â}
> > +Â Â Â} else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
> > +Â Â Â Â Â Â Â/* Master read other than start */
> >Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave,
> > -Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_WRITE_RECEIVED, &value);
> > -
> > -Â Â Â Â Â Â Â/* check the status for the last byte of the
> transaction */
> > -Â Â Â Â Â Â Ârd_status = (val >> S_RX_STATUS_SHIFT) &
> S_RX_STATUS_MASK;
> > -Â Â Â Â Â Â Âif (rd_status == I2C_SLAVE_RX_END)
> > -Â Â Â Â Â Â Â Â Â Â Âiproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂI2C_SLAVE_READ_PROCESSED, &value);
> >Â
> > -Â Â Â Â Â Â Âdev_dbg(iproc_i2c->device, "\nread value = 0x%x\n",
> value);
> > +Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> > +Â Â Â Â Â Â Âval = BIT(S_CMD_START_BUSY_SHIFT);
> > +Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> >Â Â Â Â}
> >Â
> >Â Â Â Â/* Stop */
> >Â Â Â Âif (status & BIT(IS_S_START_BUSY_SHIFT)) {
> >Â Â Â Â Â Â Â Âi2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
> &value);
> > -Â Â Â Â Â Â Âiproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
> > +Â Â Â Â Â Â Â/*
> > +Â Â Â Â Â Â Â * Enable interrupt for TX FIFO becomes empty and
> > +Â Â Â Â Â Â Â * less than PKT_LENGTH bytes were output on the SMBUS
> > +Â Â Â Â Â Â Â */
> > +Â Â Â Â Â Â Âval = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> > +Â Â Â Â Â Â Âval &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
> > +Â Â Â Â Â Â Âiproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> >Â Â Â Â}
> >Â
> >Â Â Â Â/* clear interrupt status */
> >
>