Re: [PATCH V5 08/12] perf/x86/intel: Add Icelake support

[Liang, Kan]

On 4/8/2019 11:06 AM, Peter Zijlstra wrote:
> On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
> > +static struct event_constraint *
> > +icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> > +			  struct perf_event *event)
> > +{
> > +	/*
> > +	 * Fixed counter 0 has less skid.
> > +	 * Force instruction:ppp in Fixed counter 0
> > +	 */
> > +	if ((event->attr.precise_ip == 3) &&
> > +	    ((event->hw.config & X86_RAW_EVENT_MASK) == 0x00c0))
> > +		return &fixed_counter0_constraint;
>
> Does that want to be:
>
> 		event->hw.config == X86_CONFIG(.event=0xc0)
>
> ?
>
> That is, are there really bits we want to mask in there?

For instruction event, right, we don't need mask it.
I will change it.

Thanks,
Kan

> > +
> > +	return hsw_get_event_constraints(cpuc, idx, event);
> > +}