Re: [net: PATCH] net: mvpp2: disable link IRQ waiting for IDLE frames

[Russell King - ARM Linux admin]

On Wed, Feb 27, 2019 at 06:47:32PM +0100, Marcin Wojtas wrote:
> Current version of the driver was configuring XLG MAC
> in a way to wait 3 IDLE frames before allowing for the
> link-up interrupt to be triggered. This resulted in an
> issue, preventing to detect the link change during RX
> traffic on the interface. Fix that.

What about noise sensitivity?  Does this now mean that on boards such as
Macchiatobin Single Shot or Clearfog GT9k where the serdes is connected
directly to a SFP cage, that noise on the serdes lines triggers a link
indication?

> 
> Fixes: 4bb043262878 ("net: mvpp2: phylink support")
> Signed-off-by: Marcin Wojtas <mw@xxxxxxxxxxxx>
> ---
>  drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index 16066c2..f1378f9 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -4532,8 +4532,7 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
>  		ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
>  
>  	ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
> -	ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
> -		 MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
> +	ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC;
>  
>  	writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
>  	writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
> -- 
> 2.7.4
> 
> 
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-- 
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