Re: [PATCH] EDAC, dmc520:: add DMC520 EDAC driver

[Borislav Petkov]

On Wed, Jan 23, 2019 at 06:36:23PM +0000, James Morse wrote:
> > Would like to know what's the impact if this error happens, and how to fit it
> > with current reporting in EDAC core.
> 
> At a guess the interrupt triggers when link_err_count increases. (link_err has
> an overflow bit, so the interrupt must be related to a counter).
> 
> If we could associate a link with a layer in edac, we could report errors
> against that point. But I've no idea how 'links' correspond with 'ranks and banks'!

Well, I have no clue what kind of links you guys are talking but if
those are per-chance coherent links used by cores to communicate in a
coherent fabric, or cores and devices, what would showing those errors
to the user bring ya?

Or are ya talking about different kinds of links?

In any case, the first question to ask would be, can some agent or the
user do something with the information that X or Y link errors happened?

If not, then why bother?

If yes, then that's a different story.

-- 
Regards/Gruss,
    Boris.

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