RE: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Hi Tudor,

> -----Original Message-----
> From: Tudor Ambarus [mailto:tudor.ambarus@xxxxxxxxxxxxx]
> Sent: Wednesday, September 19, 2018 10:00 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@xxxxxxx>; linux-
> mtd@xxxxxxxxxxxxxxxxxxx; linux-spi@xxxxxxxxxxxxxxx
> Cc: boris.brezillon@xxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> marek.vasut@xxxxxxxxx; frieder.schrempf@xxxxxxxxx;
> cyrille.pitchen@xxxxxxxxxx; computersforpeace@xxxxxxxxx
> Subject: Re: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON
> flash
> 
> Hi,
> 
> On 09/19/2018 07:50 AM, Yogesh Gaur wrote:
> > Some MICRON related macros in spi-nor domain were ST.
> > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> >
> > Added entry of MFR Id for Micron flashes, 0x002C.
> >
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@xxxxxxx>
> > ---
> >  drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
> >  include/linux/mtd/cfi.h       | 1 +
> >  include/linux/mtd/spi-nor.h   | 3 ++-
> >  3 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index f028277..33a55bc 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const
> struct flash_info *info,
> >  	u8 cmd;
> >
> >  	switch (JEDEC_MFR(info)) {
> > +	case SNOR_MFR_ST:
> 
> We should mark switch cases where we are expecting to fall through, so that we
> will be prepared when enabling -Wimplicit-fallthrough.

Please explain more, not able to get this comment. Sorry for ignorance.

> 
> >  	case SNOR_MFR_MICRON:
> >  		/* Some Micron need WREN command; all will accept it */
> >  		need_wren = true;
> > @@ -1096,7 +1097,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd,
> loff_t ofs, uint64_t len)
> >  	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> >  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
> > SPI_NOR_QUAD_READ) },
> >
> > -	/* Micron */
> > +	/* Micron <--> ST Micro */
> >  	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K |
> SPI_NOR_QUAD_READ) },
> >  	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64,
> SPI_NOR_QUAD_READ) },
> >  	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64,
> SPI_NOR_QUAD_READ) },
> > @@ -2502,6 +2503,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
> >  			params->quad_enable = macronix_quad_enable;
> >  			break;
> >
> > +		case SNOR_MFR_ST:
> >  		case SNOR_MFR_MICRON:
> >  			break;
> >
> > @@ -2876,8 +2878,9 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name,
> >  	mtd->_resume = spi_nor_resume;
> >
> >  	/* NOR protection support for STmicro/Micron chips and similar */
> > -	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > -			info->flags & SPI_NOR_HAS_LOCK) {
> > +	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
> > +	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > +	    info->flags & SPI_NOR_HAS_LOCK) {
> >  		nor->flash_lock = stm_lock;
> >  		nor->flash_unlock = stm_unlock;
> >  		nor->flash_is_locked = stm_is_locked; diff --git
> > a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index
> > 9b57a9b..cbf7716 100644
> > --- a/include/linux/mtd/cfi.h
> > +++ b/include/linux/mtd/cfi.h
> > @@ -377,6 +377,7 @@ struct cfi_fixup {
> >  #define CFI_MFR_SHARP		0x00B0
> >  #define CFI_MFR_SST		0x00BF
> >  #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
> > +#define CFI_MFR_MICRON		0x002C /* Micron */
> 
> Can you point us to a datasheet to verify the id?
> 

Currently data sheet of this flash is under NDA, I have asked Micron guys to provide the public link of this data sheet.

--
Regards
Yogesh Gaur.

> Best,
> ta
> 
> >  #define CFI_MFR_TOSHIBA		0x0098
> >  #define CFI_MFR_WINBOND		0x00DA
> >
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index c922e97..f43bfc5 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -23,7 +23,8 @@
> >  #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
> >  #define SNOR_MFR_GIGADEVICE	0xc8
> >  #define SNOR_MFR_INTEL		CFI_MFR_INTEL
> > -#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron
> */
> > +#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
> > +#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/* Micron */
> >  #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
> >  #define SNOR_MFR_SPANSION	CFI_MFR_AMD
> >  #define SNOR_MFR_SST		CFI_MFR_SST
> >